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| 研究生： |
游敦皓 |
|---|---|
| 論文名稱： |
以快速傅立葉轉換為基礎之相位展開法則在可程式化系統晶片上之實現 |
| 指導教授： | 黃文吉 |
| 學位類別： |
碩士 Master |
| 系所名稱： |
資訊工程學系 Department of Computer Science and Information Engineering |
| 論文出版年： | 2010 |
| 畢業學年度： | 98 |
| 語文別： | 中文 |
| 論文頁數： | 64 |
| 中文關鍵詞： | 系統晶片設計 、可程式化邏輯閘陣列 、軟硬體整合設計 、相位展開技術 |
| 英文關鍵詞： | SoPC, FPGA, Hardware Software Co-Design, Phase Unwrapping |
| 論文種類： | 學術論文 |
| 相關次數： | 點閱：40 下載：4 |
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本論文提出一個以快速傅立葉轉換為基礎的相位展開法則硬體電路架構，此相位展開硬體電路架構的功能在於加速數位全像顯微鏡（Digital Holographic Microscopy, DHM）的相位展開運算。本架構會依據一個以快速傅立葉轉換為基礎的相位展開演算法則來設計並且實作硬體電路以計算出一個最小平方誤差解（minimum squared error solution）。硬體架構中包含四個主要單元：轉換前單元、快速傅立葉轉換單元、轉換後單元以及嵌入式記憶體，在架構中利用嵌入式記憶體當作暫存空間搭配上其他三個單元的運算來達到加速電路計算的效果。為了驗證本論文提出的硬體架構的正確性，會將本硬體電路設計成客製化的電路放入system on programmable chip（SoPC）系統來實際上測量系統的效能。實驗的結果顯示本論文提出的硬體電路架構可以有效的減少相位展開運算所需要花費的時間以及硬體資源的消耗量，適合於設計嵌入式的DHM系統。
This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM). An FFT-based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is used as a custom user logic in a system on programmable chip (SoPC) for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while attaining excellent performance for designing an embedded DHM system.
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[10] Hauck, S., and Dehon, A., Reconfigurable Computing, Morgan Kaufmann, 2008.
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[12] S. Braganza and M. Leeser, “Implementing Phase Unwrapping Using Field Programmable Gate Arrays or Graphics Processing Units : A Comparison,” High-Performance Reconfigurable Computing Technology and Applications, pp. 1-10, November 2008.
