簡易檢索 / 詳目顯示

回結果列表
研究生： 王冠勳
Kuan-Hsun Wang
論文名稱： 應用於音頻之二階具預先偵測3位元37位階動態量化器之三角積分調變器設計與實現
Design and Implementation of Second-Order ΔΣ Modulator with 3-Bit, 37-Level Pre-Detective Dynamic Quantization for Audio Application
指導教授： 郭建宏
Kuo, Chien-Hung
學位類別： 碩士
Master
系所名稱： 電機工程學系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 中文
論文頁數： 121
中文關鍵詞： 預先偵測器 、模組選擇器 、動態量化器 、三角積分調變器 、類比數位轉換器 、分散式回授串聯積分器 、動態元件匹配
英文關鍵詞： Pre-Detector, Mode Selector, Dynamic Quantizer, Delta-Sigma Modulator, Analog-to-Digital Converter, CIFB, Dynamic Element Matching
論文種類： 學術論文
相關次數： 點閱：93  下載：22 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 在當今製程的進步下，積體電路設計已進入奈米時代。拜科技所賜，可攜式行動通訊已成為目前生活的必需品，所以低功率高效能電路的設計越來越重要。
    以低功率高效能為目標，在眾多類比數位轉換器中，最屬三角積分調變器對類比電路元件的非理想特性較不敏感。且當今消費者對產品的需求，所以使得三角積分調變器非常適合用於高解析度的應用。

    本篇論文中，提出一個具有動態量化功能的三角積分調變器架構，使3位元的量化器可以達到37個位階的量化功能。在此架構中，利用預先偵測的電路技術，適時調整量化器的可量化範圍，以增加可量化的階數，並大幅減少高位元量化下所需的元件數。藉由此技術，三角積分調變器不僅可以降低功率與面積的消耗，還可以大幅提升類比數位信號轉換的解析度。在TSMC 0.18 mm 1P6M標準CMOS製程下，此預先偵測動態量化之三角積分調變器在1.8 V的供應電壓，以及25 kHz的頻寬範圍內，測得的信號雜訊失真比為101.2 dB，動態範圍為102dB，功率消耗為1.68 mW。晶片面積不包含PAD的大小為3.06 mm2。

    另外也提出了一個具雜訊移頻動態元件匹配電路用以處理數位至類比路徑所產生的雜訊。傳統上在處理此雜訊會使用動態元件匹配電路來完成，但無法像三角積分調變器在處理量化雜訊一樣具有雜訊移頻的方式把量化雜訊推至高頻。所提出的想法能使DAC路徑所產生的雜訊具有雜訊移頻的能力，降低雜訊在低頻的能量，使得系統訊號雜訊比的表現較好。

    In this paper, a high-resolution delta-sigma modulator with a pre-detective dynamic quantizer is proposed. A 37-level quantization can be achieved by using only a 3-bit quantizer in the proposed dynamic quantizer. In the proposed structure, a signal detector is added at the input of the presented modulator to pre-detect the magnitude of the sampled input and switch the dynamic quantizer to the corresponding quantization range. With the proposed technique, the quantization level can be greatly increased, and the number of comparators will hence be substantially reduced for a high-level quantization. The resulting resolution of delta-sigma modulators can thus be significantly promoted without consuming much power and area. The proposed delta-sigma modulator is implemented in a TSMC 0.18 μm 1P6M CMOS process. The signal-to-noise plus distortion ratio is 101.2 dB and dynamic range is 102 dB in a signal band of 25 kHz. The power consumption is 1.68 mW at a 1.8 V supply voltage.

    A dynamic element matching with noise shaping technique in delta-sigma modulator is proposed. The proposed structure can shape the feedback noise to high frequency just like the delta sigma modulator shape the quantization noise. The architecture can substantially reduce the in-band noise and get much better performance.

    摘　　要 I ABSTRACT III 誌　　謝 V 目　　錄 VII 圖　目　錄 X 表　目　錄 XV 第一章 緒論 1 1.1 研究動機與背景 1 1.2 積體電路設計流程 2 1.3 類比數位轉換器之應用與比較 3 1.4 論文大綱與概要 3 第二章 三角積分調變器概論之效能指標與架構比較 5 2.1 前言 5 2.2 效能指標 6 2.2.1 動態範圍 6 2.2.2 訊號雜訊比 7 2.2.3 訊號雜訊失真比 7 2.2.4 解析度 7 2.2.5 無雜波干擾之動態範圍 8 2.3 量化器與量化誤差 8 2.3.1 一位元量化器 8 2.3.2 多位元量化器 9 2.3.3 量化誤差的產生 12 2.4 超取樣 14 2.5 雜訊移頻 15 2.5.1 一階雜訊移頻 17 2.5.2 二階雜訊移頻 19 2.5.3 高階雜訊移頻 22 2.6 動態量化器 25 2.7 動態元件匹配 26 2.8 章節結論 26 第三章 具預先偵測架構之三角積分調變器的基本電路元件設計 27 3.1前言 27 3.2交換電容式電路 27 3.2.1 非反向積分器 27 3.2.2 反向積分器 29 3.3 開關 30 3.3.1 NMOS與PMOS開關 31 3.3.2 傳輸閘開關 32 3.3.3 時脈增強開關 32 3.3.4 靴帶式開關 33 3.4 運算放大器 36 3.4.1 運算放大器推導 36 3.4.2 輸入對動作原理 37 3.4.3 運算放大器設計要求 38 3.5 共模準位電路 41 3.6 偏壓電路 43 3.7 比較器電路 43 3.8 量化器 44 3.9 動態元件匹配電路 45 3.9.1 資料權重平均電路 46 3.9.2 時脈平均演算法電路 47 3.10 時脈產生器 49 3.11 章節結論 49 第四章 應用於音頻之二階具預先偵測3位元37位階動態量化器之三角積分 調變器設計與實現 51 4.1 前言 51 4.2傳統快閃式量化器之架構考量 52 4.3具預先偵測動態量化器之設計想法 52 4.3.1動態量化器操作想法 53 4.3.2動態量化器原理架構圖 55 4.4具預先偵測動態量化器之等效線性MATLAB模擬 56 4.4.1具預先偵測動態量化之三角積分調變器線性架構 56 4.4.2等效線性架構MATLAB模擬結果 58 4.5內部電路的非理想效應 60 4.5.1時脈抖動 60 4.5.2熱雜訊 61 4.5.3電荷注入 63 4.5.4時脈饋入 66 4.5.5閃爍雜訊 67 4.5.6運算放大器之有限增益需求 68 4.5.7運算放大器之輸出擺幅線性度 69 4.5.8運算放大器之閉迴路負載電容需求 70 4.5.9運算放大器之有限單一增益頻寬、迴轉率和最小電流需求 71 4.5.10三角積分調變器考慮非理想效應 74 4.6具預先偵測動態量化器之設計與電路實現 76 4.6.1預先偵測器 76 4.6.2模組選擇器 77 4.6.3動態量化器 78 4.7具預先偵測動態量化器之三角積分調變器設計與電路實現 79 4.7.1三角積分調變器設計與電路實現 79 4.7.2運算放大器之設計 81 4.7.3三角積分調變器模擬結果 82 4.8電路佈局與實現 83 4.9封裝和鎊線效應 87 4.10晶片量測與實驗結果 88 4.10.1輸入訊號與終端電路 88 4.10.2供應電壓源電路的產生-高電位 89 4.10.3供應電壓源電路的產生-低電位 90 4.10.4濾波槽電路 90 4.10.5量測結果 90 4.11章節結論 101 第五章 應用於音頻之二階具雜訊移頻動態元件匹配之三角積分調變器設計 103 5.1 前言 103 5.2 具雜訊移頻動態元件匹配電路之設計想法 103 5.2.1 具一階雜訊移頻動態元件匹配電路之概念 104 5.2.2 具N階雜訊移頻動態元件匹配電路之概念 104 5.2.3 具一階雜訊移頻動態元件匹配電路之架構 105 5.3 具雜訊移頻動態元件匹配電路之等效線性MATLAB模擬 105 5.3.1 增加動態範圍與系統穩定度考量 107 5.4 具雜訊移頻動態元件匹配電路之三角積分調變器設計與電路實現 110 5.5 章節結論 111 第六章 總結與未來展望 113 6.1 總結 113 6.2 未來展望 114 參　考　文　獻 115 作　者　簡　歷 119 學　術　成　就 121

    [1] J. M. de la Rosa, “Sigma-Delta modulators: Tutorial overview, design guide, and state-of-the-art survey,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 1, pp. 1–21, Jan. 2011.
    [2] T. Yoshida, M. Sasaki, and A. Iwata, “A 1-V supply successive approximation ADC with rail-to-rail input voltage range,” IEEE Int. Symp. Circuits Syst., May 2005, pp. 192-195.
    [3] D. A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
    [4] R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, Second Edition, Wiley, IEEE Press, 2008.
    [5] J. Silva, U. K. Moon, J. Steensgaard, and G. C. Temes, “Wideband Low-Distortion Delta-Sigma ADC Topology,” Electron. Lett., vol. 37, pp. 737-738, Jun. 2001.
    [6] T. Ritoniemi, T. Karema, and H. Tenhunen, “The Design of Stable High Order 1-Bit Sigma-Delta Modulators,” in Proc. IEEE Intel. Symp. Circuits Syst., May 1990, pp. 3267-3270.
    [7] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters: New York: Wiley, 2004.
    [8] T. Tille, J. Sauerbrey, and D. Schmitt-Landsiedel, “A Low-Voltage MOSFET-only Modulator for Speech Band Applications Using Depletion-Mode MOS-Capacitors in Combined Series and Parallel Compensation,” in Proc. IEEE Intel. Symp. Circuits Syst., May 2001, pp-376-379.
    [9] J. Sauerbrey, T. Tille, D. S. Landsiedel, and R. Thewes, “A 0.7-V MOSFET-Only Switched-Opamp Modulator in Standard Digital CMOS Technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp.1662-1669 Dec. 2002.
    [10] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched op amp circuits,” Electron. Lett., vol. 35, no. 1, pp. 8-10, Jan. 1999.
    [11] A. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal, “Low-Voltage Super Class-AB CMOS OTA Cell with Very High Slew Rate and Power Efficiency,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1068-1077, May. 2005.
    [12] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-uW 88-dB audio sigma-delta modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1809-1818, Nov. 2004.
    [13] Da-Huei Lee and Tai-Haur Kuo, “Advancing Data Weighted Averaging Technique for Multi-Bit Sigma-Delta Modulators”, IEEE Trans. Circuits Syst. II, Express Briefs, vol. 54, no. 10, pp. 838-842, Oct. 2007.
    [14] L. R. Carley. “A Noise-Shaping Coder Topology for 15+ Bit Converters,” IEEE J. Solid-State Circuits. vol. 24, no. 2, April. 1989.
    [15] J. Ron, S. Byun, Y. Choi, H. Roh, Y. G. Kim, and J. K. Kwon, “A 0.9-V 60-μW 1-Bit Fourth-Order Delta–Sigma Modulator with 83-dB Dynamic Range,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 361–370, Feb. 2008.
    [16] A. Gharbiya, and D. A. Johns, “A 12-bit 3.125 MHz Bandwidth 0-3 MASH Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2010–2018, July. 2009.
    [17] R. Schreier, and G.C. Temes, Understanding delta-sigma data converters, NJ: IEEE Press, 2005.
    [18] L. Dorrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig, ”A 3-mW 74-dB SNR 2-MHz continuous-time Delta-Sigma ADC with a tracking ADC quantizer in 0.13-um CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 2416-2426, Dec. 2005.
    [19] S. Pesenti, P. Clement and M. Kayal, “Reducing the Number of Comparators in Multi-Bit  Modualtors,” IEEE Trans. Circuits Syst. I, vol. 55, no. 4, pp. 1011-1022, May. 2008.
    [20] Y. Yang, T. Sculley, and J. Abraham, “A single die 124dB stereo audio delta sigma ADC with 111dB THD,” in Proc. European Solid-State Circuits Conf., pp. 252-255, Sept. 2007.
    [21] F. Colodro and A. Torralba, “Continuous-time sigma-delta modulator with a fast tracking quantizer and reduced number of comparators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 9, pp. 2413–2425, Sep. 2010.
    [22] S. Pesenti, P. Clement, and M. Kayal, “Reducing the number of comparators in Multibit Delta Sigma Modulators,” IEEE Transactions on Circuits and Systems I, vol. 55, no. 4, pp. 1011-1022, May 2008.
    [23] A. Gharbiya, and D. A. Johns, “On the implementation of input feedforward delta-sigma modulators,” IEEE Trans. Circuits Syst. I, vol. 53, no. 6, pp. 453-457, 2006.
    [24] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc. New York, NY, USA, 2001.
    [25] H. A. C. T. Mervyn, “A novel architecture for reducing the sensitivity of multibit sigma-delta ADCs to DAC nonlinearity,” in Proc. Int. Symp. Circuits Syst., May 1995, vol. 1, pp. 17-20.
    [26] J. Chen and Y. P. Xu, “A novel noise shaping DAC for multi-bit sigma-delta modulator,” IEEE Trans Circuits Syst. II, Exp. Briefs, vol. 53, no. 5, pp. 344-348, May 2006.
    [27] Alex Jianzhong Chen and Y. P. Xu, “Multi delta-sigma modulator with noise-shaping dynamic element matching,” IEEE Trans Circuits Syst. I, vol. 56, no. 6, June 2009.
    [28] Mohamed Aboudina and Behazad Razavi, “A new DAC mismatch shaping technique for sigma-delta modulators, ” IEEE Trans Circuits Syst. II, vol. 57, no. 12, December 2010.
    [29] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS,” IEEE Journal Solid-State Circuits, vol. 39, no. 11, pp.1809 - 1818, Nov. 2004.
    [30] G. Ahn et al., “A 0.6 V 82 dB DS audio ADC using switched-RC integrators,” in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 166–167.
    [31] J. Goes, B. Vaz, R. Monteiro, and N. Paulino, “A 0.9 V DS modulator with 80 dB SNDR and 83 dB DR using a single-phase technique,” in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 74–75.
    [32] K.-P. Pun, S. Chatterjee, and P. R. Kinget, “A 0.5-V 74-dB SNDR 25-kHz continuous-time delta-sigma modulator with a return-to-open DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 496–507, Mar. 2007.
    [33] J. Roh, S. Byun, Y. Choi, H. Roh, Y.G. Kim, and J.K. Kwon, “A 0.9-V 60-μW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 361–370, Feb. 2008.
    [34] H. Park, K.g Nam, D. K. Su, K. Vleugels, and B. A. Wooley, “A 0.7-V 870-uW Digital-Audio CMOS Sigma-Delta Modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1078–1088, Apr. 2009.
    [35] Y. Chae, and G. Han, “Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 458–472 Feb. 2009.
    [36] Chien-Hung Kuo, Deng-Yao Shi, and Kang-Shuo Chang, "A Low-Voltage Fourth-Order Cascade Delta-Sigma Modulator in 0.18-μm CMOS," IEEE Transactions on Circuits and Systems I, vol. 57, no. 9, pp. 2450-2461, Sep. 2010.
    [37] J. Zhang et al., “A 0.6-V 82-dB 28.6-μW continuous-time audio Delta-Sigma modulator,” IEEE J. Solid-State Circuits, vol. 46, no. 10, pp. 2326–2335, Oct. 2011.
    [38] H. Wang et al., “0.9 V 58 mW 92 dB SNDR audio DS modulator with high efficiency low noise switched-opamp and novel DWA technique,” Electronics Letters, vol. 47, no. 4, pp. 237-239, Feb. 2011.
    [39] Z. Yang, L. Yao, Y. Lian, “A 0.5-V 35-μW 85-dB DR Double-Sampled DS Modulator for Audio Applications,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 722-735, Mar. 2012.
    [40] F. Michel and M. Steyaert, “A 250 mV 7.5 W 61 dB SNDR CMOS modulator using a near-threshold-voltage-biased CMOS inverter technique,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 709–721, Mar. 2012.
    [41] L. Liu, D. Li, L. Chen, Y. Ye, and Z. Wang, “A 1-V 15-Bit Audio DS -ADC in 0.18 μm CMOS,” IEEE Trans. on circuits and systems I, Reg. papers, vol. 59, no.5, pp. 915-925, MAY. 2012.
    [42] G.-M. Sung, C.-P. Yu, T.-W. Hung, and H.-Y. Hsieh, “Mixed-mode chip implementation of digital space svpwm with simplified-cpu and 12-bit 2.56 ms/s switched-current delta-sigma adc in motor drive,” IEEE Trans. Power Electron., vol. 27, pp. 916–930, 2012.

    下載圖示
    QR CODE