Sn-8Zn-3Bi覆晶組裝製程及其電遷移研究

本實驗中，以電鍍方式製程生長Sn-8Zn-3Bi覆晶銲錫凸塊。銲錫凸塊以兩階段式之電鍍方式，先鍍上共晶錫鋅再鍍上鉍之方法，其表面之鉍層可防止鋅的氧化。迴銲後，鉍會熔入錫鋅中形成三元的合金。此方式可以克服電鍍液中，一次共鍍三元合金之困難技術。電遷移之實驗，研究Sn-8Zn-3Bi覆晶銲錫接點在120 oC及150oC下不同之電流密度之條件。其結果，在負極端及正極端界面上，分別生成孔洞和凸起物。此外，在負極端之介金屬化合物會因為電遷移之影響，而轉變成富錫相。且由於極化之現象，在正極端之介金屬化合物的厚度會大於負極端之介金屬化合物。試片在120 oC及4.5 x 104 A/cm2之平均電流密度下，試片在117小時後失效，且在負極端上可發現清晰之孔洞存在。同時，此試片在邊界處有融熔之銲錫球存在。利用電流密度之模擬分析實驗，發現在覆晶接點中，其電流密度並非均勻分佈且有電流叢聚之現象。這樣的分析結果指出，電流密度之叢聚現象，將會升高電流密度，並造成嚴重的熱焦耳效應和電遷移破壞的發生。

關鍵字

無鉛銲錫；電子構裝；電鍍；電遷移

並列摘要

In flip chip packaging technology, using electroplating to develop the flip chip solder bumps of Sn-8Zn-3Bi in this study. Investigating two-steps electroplating method, to plate the eutectic Sn-Zn and Bi in order. The Bi layer could cover the surface of Sn-Zn alloy and avoid the oxidation of the Zn. After the reflow, Bi will melt and dissolve into the eutectic Sn-Zn, and then formed the ternary alloy. This method could overcome the difficulty of the co-plating the ternary alloy at a time. Electromigration of Sn-8Zn-3Bi flip chip solder bumps on Cu has been studied at 120 oC and 150 oC with different current density. Formation of voids and hillocks at the cathode and anode, respectively, has been observed. In addition, a Sn-rich phase has replaced some part of the intermetallic compound of Cu-Zn (γ) which formed between the solder and the Cu pad in the anode side. Due to the polarity effect, the thickness of the intermetallic compound at the anode is thicker than at the cathode. The solder joint fails after 117hrs under 120 oC with an average current density 4.5 x 104 A/cm2 and voids formation at the cathode can clearly be seen after polishing. It is the melting at the edge of the bump that fails the solder. The simulation of the current density distribution indicates that the current density is not uniformly distributed and the current crowding occurs inside the bump. The results indicate that the increase of current density associated with joule heating has affected and enhanced the damage in the solder joint under electromigration.

並列關鍵字

lead-free solder ； electronics packaging ； electroplating ； electromigration

參考文獻

2. C. A. Harper, Electronic Packaging and Interconnection Handbook, McGraw-Hill, 2000.

3. R. R. Tummala, Fundamental of Microsystems Packaging, McGraw-Hill, 2001.

6. C. S. Chang, A. Oscilowski, and R. C. Bracken, ”Future Challenges in Electronics Packaging”, Circuits & Devices, 1998, pp.45-54.

7. S.H. Fan, Y.C. Chan, C.W. Tang, JKL Lai, “Aging studies of PBGA solder joints reflowed at different conveyor speeds “, Transactions on Advanced Packaging, Vol. 24, 2001, pp.46-492.

8. J. H. Okura, S. Shetty, B. Ramakrishnan, A. Dasgupta, J. F. J. M. Caers, “Guidelines to select underfills for flip chip on board assemblies and compliant interposers for chip scale package assemblies”, Microelectronics Reliability, Vol. 40, 2000, pp.1173-1180.

國際替代計量

Sn-8Zn-3Bi覆晶組裝製程及其電遷移研究

全文下載

主題瀏覽