低功率晶片網路交換器架構設計

在先進的超大型積體電路設計當中，晶片系統(system-on-a-chip)是必然的趨勢。隨著製程不斷地縮小，晶片系統中各個IP之間的訊息交換變成是晶片設計上的一大挑戰，也是設計上最主要的考慮因素，為了克服這些訊息交換所造成的瓶頸，有許多研究提出以晶片網路(Network-on-chip, NoC)的方式提供可延伸並且可靠的晶片通訊方式。在晶片網路架構中，交換器(switch)是最重要的組成元件，所有晶片網路的特性以及其所提供的功能都必須藉由設計以及實現一個交換器架構來達成。在本篇論文中我們提出了一個在二維網格拓墣(2-D mesh topology)上的低功率交換器架構，利用減少緩衝器的(buffer)的使用個數以及調整大小，本篇研究可以有效的降低晶片網路的功率消耗，並且在此交換器架構當中，所提出的緩衝架構也有效的防止死結(deadlock)的發生。在本論文的實驗中，數據顯示和先前的交換器架構設計比較，我的交換器可使晶片網路架構降低約60%的功率消耗。

關鍵字

低功率；晶片網路；晶片系統；交換器架構

並列摘要

System-on-a-chip is a trend of modern circuit design. However, with the technology scales down, the inter-communication between IP cores becomes main challenge of SoC design. To overcome the communication problem, Network-on-Chip (NoC) is proposed to provide scalable and reliable on-chip communication. NoC switch (or so-called router) is the most important component of a NoC architecture, and all functions and properties of a NoC is carried out by designing and implementing a switch architecture. In this thesis, a low-power 2-buffer best-effort NoC switch architecture for 2D mesh NoC topology is proposed. By reducing the number of inside buffer and adjusting the buffer size, my work can effectively reduce NoC power consumption. Furthermore, the proposed architecture is free from deadlock since a novel buffering architecture is also proposed in this thesis. Experimental results show that the proposed architecture can save NoC switch power consumption up to 60% comparing with previous switch architecture.

並列關鍵字

Low Power ； Network-on-Chip ； System-on-Chip ； switch architecture

參考文獻

[1] Paul Wielage and Kees Goossens, “Network on Silicon: Blessing or Nightmare?”, In Proc. of Euromicro Symposium on Digital System Design, pp. 196-200, Sept. 2002.

[2] Pierre Guerrier and Alain Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnections”, In Proc. of Design, Automation and Test in Europe Conference and Exhibition, pp. 250-256, March, 2000.

[3] William J. Dally and Brian Towles, “Route Packets, Not Wires: On-Chip Interconnection networks”, In Proc. of DAC, pp. 684-689, 2001.

[4] K. C. Saraswat et al., “Technology and Reliability Constrained Future Copper Interconnects – Part II: Performance Implications,” IEEE Trans. on Electron Devices, vol. 49, no. 4, pp. 598-604, Apr. 2002.

[5] D. Sylvester and K. Keutzer, “Impact of Small Process Geometries on Microarchitectures in Systems on a Chip,” in Proc. of IEEE, vol. 89, no. 4, pp. 467-489, Apr. 2001.

國際替代計量

低功率晶片網路交換器架構設計

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