- 學位論文
使用CMOS與LTPS製程設計與實現具有充電泵校正之時脈產生器
Design and Implementation of Clock Generators with Charge Pump Calibration in CMOS/LTPS Technology
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摘要
隨著製程科技快速的演進，越來越多類比與數位電路被整合到單一晶片上，同步化的控制相對於非同步來說較為簡單且更常被採用，然而，時脈的特性通常會大幅地影響系統的效能，此時脈的產生通常由一個鎖相迴路或延遲鎖定迴路來實現，因此，設計一個鎖相迴路或延遲鎖定迴路來滿足特定的需求是相當重要的。首章介紹在鎖相迴路或延遲鎖定迴路中一些時脈的非理想現象與限制，主要針對五個主題：(1)充電泵電流不匹配；(2)錯誤鎖定與諧波鎖定；(3)時間放大；(4)相位雜訊；(5)時脈的責任周期。 第二章提出一個充電泵自我校正的鎖相迴路來改善充電泵的電流不匹配，與一個阻抗提升技巧來增加充電泵的輸出阻抗，此鎖相迴路以3um低溫多晶矽薄膜電晶體製程來實現，晶片面積為18.9mm^2，在8.4V的電源下，操作頻率從5.6MHz至10.5MHz，在10.5MHz下，功率消耗為7.81mW。 第三章提出一個以環型振盪器為基礎的相位誤差累積方法，並用在一個延遲鎖定迴路來解決充電泵電流不匹配，另外用一個類比相位偵測器來避免錯誤與諧波鎖定，此延遲鎖定迴路以CMOS 0.18um製程來實現，晶片面積為0.7mm^2，在1.8V的電源與750MHz的操作頻率下，功率消耗為16.2mW。 第四章實現一個以環型振盪器為基礎的高增益與高線性度時間放大器，並包括一個閉迴路增益控制。此時間放大器應用到一個鎖相迴路來降低頻寬內的相位雜訊，而第三章所提的充電泵校正技術也被用在這個鎖相迴路中。時間放大器與鎖相迴路皆以CMOS 0.18um製程來實現，時間放大器的晶片面積為0.438mm^2，在1.8V的電源與10MHz的操作頻率下，功率消耗為25.8mW。鎖相迴路的晶片面積為0.9801mm^2，在1.8V的電源與1GHz的操作頻率下，功率消耗為35.24mW。 第五章介紹一個全數位可調責任周期延遲鎖定迴路，主要討論時脈的責任周期與解決錯誤與諧波鎖定，此延遲鎖定迴路以CMOS 0.18um製程來實現，核心面積為0.054mm^2，在1.8V的電源與800MHz的操作頻率下，一個輸出時脈的功率消耗為2.7mW。此外，本章舉了一個二階三角積分調變器作為數位責任周期校正的例子，此調變器是以3um低溫多晶矽薄膜電晶體製程來實現，晶片面積為52.25mm^2，在11.2V的電源與350kHz的取樣頻率下，功率消耗為158mW。 最後，第六章針對本論文作總結並提出一些未來的研究方向。
並列摘要
As the process technology is rapidly scaled down, more and more analog and digital circuits are integrated in a single chip. A synchronous control is simple and preferred compared with the asynchronous one. However, the characteristics of a clock usually influence the system performance substantially. This clock generation is usually realized by a phase-locked loop (PLL) or delay-locked loop (DLL). Therefore, to design a PLL or DLL to satisfy certain requirements is really important. The first chapter introduces some imperfections and limitations of the clock in a PLL or DLL. They focus on five topics: (1) current mismatch in charge pump; (2) false locking and harmonic locking; (3) time amplification; (4) phase noise; (5) duty cycle of a clock. Chapter 2 proposed a PLL with self-calibrated charge pumps to improve the current mismatch in charge pump. And an impedance boosting technique is proposed to increase the output impedance of the charge pump. This PLL has been fabricated in a 3µm low-temperature poly-silicon thin-film transistor (LTPS-TFT) technology. It operates from 5.6MHz to 10.5MHz at a supply of 8.4V. Its area is 18.9mm^2 and consumes 7.81mW at 10.5MHz. In chapter 3, a ring-oscillator based phase error accumulation method is proposed and applied to a DLL for charge pump calibration. An analog phase detector is proposed to avoid the false and harmonic locking. This DLL has been fabricated in a CMOS 0.18µm technology. Its area is 0.7mm^2 and consumes 16.2mW at 750MHz from a supply of 1.8V. In chapter 4, a ring-oscillator based time amplifier is proposed to achieve the high-gain and high-linearity. And a closed-loop gain control is included. This time amplifier is applied to a PLL to reduce the in-band phase noise of the PLL. Besides, the charge pump calibration technique in chapter 3 is also adopted in this PLL. The TA and PLL have been simulated in a CMOS 0.18µm technology. The chip area of the TA is 0.438mm^2 and consumes 25.8mW at 10MHz from a supply of 1.8V. The chip area of the PLL is 0.9801mm^2 and consumes 35.24mW at 1GHz from a supply of 1.8V. Chapter 5 introduces an all-digital DLL with adjustable duty cycle. It discussed the duty cycle of a clock and solves the false and harmonic locking. This DLL has been fabricated in a CMOS 0.18µm technology. Its core area is 0.054mm^2 and consumes 2.7mW with one output clock at 800MHz from a supply of 1.8V. Besides, this chapter gives a second-order sigma-delta modulator (SDM) as an example about digital duty cycle calibration. This modulator has been fabricated in a 3µm LTPS-TFT technology. Its area is 52.25mm^2 and consumes 158mW at 350kHz sampling clock from a supply of 11.2V. Finally, chapter 6 gives the conclusion of this dissertation and some interesting research aspects for future work are described.
參考文獻
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延伸閱讀
- 許世龍（2009）。具有功率因數修正功能之交錯式CC-CV兩階段充電器的研製〔碩士論文，國立臺北科技大學〕。華藝線上圖書館。https://doi.org/10.6841/NTUT.2009.00188
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- Wu, K. I. (2016). 具高速適應性控制技術之電流模式電源管理積體電路設計與實現 [doctoral dissertation, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU201603602
- Hung, C. C. (2005). Design of CMOS Delay-Locked Loop for clock generator applications [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2005.02492
- Lo, Y. L. (2008). Design and Implementation of CMOS High-Performance Low-Voltage Clock Synchronization Circuits [doctoral dissertation, National Central University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0031-0207200917352921