一個利用時間軸轉換技巧的低功率導管式類比數位轉換器

A Low Power Pipeline ADC Using Time-Domain Transfer Technique

莊郁暐(Yu-Wei Chuang)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201603020

摘要

本論文提出一個十位元每秒3億次之導管式類比至數位轉換器，為了解決運算放大器在先進製程難以設計並且功率消耗過大，同時時域訊號的解析度於先進製程更加準確，所以設計成利用將電壓訊號轉換成時域訊號來做量化，避開使用運算放大器，並且將電壓相減之部分移動至時域信號相減，以解決比較器之延遲造成之電壓溢出的問題
論文設計之類比至數位轉換器主面積為0.694mm2, 模擬結果可達到9.49的有效位元，同時功率消耗為5.2毫瓦，FoM約為22fJ/conversion-step. 但是因為設計時並沒有考慮好噪音干擾的問題，實際做出來之晶片之有效位元低於5，因此本論文後面會進行有關噪音干擾之分析以及改進方法的討論。

關鍵字

導管式類比至數位轉換器 ； 時域訊號 ； 比較器 ； 電壓溢出 ； 噪音干擾

並列摘要

This thesis proposes a 10bit, 300MHz pipeline ADC. Due to the design difficulty in advanced process and large power consumption of operation amplifier(opamp). The proposed work wants to avoid using operation amplifier. At the same time, the time resolution in advanced process becomes more accuracy. So the time domain signal rather than voltage domain signal is used in the proposed work to do the signal process. Normally, the input signal and reference voltage is subtracted in voltage domain. In this thesis, the subtraction is realized in time domain to avoid the overshoot problem due to the delay of comparator.
The active area of the proposed work is about 0.694mm2. The ENOB can reach 9.49bit in post-simulation, whose power consumption is 5.2mW and FoM is 22fJ/conversion-step. Unfortunately, the noise of the proposed work was not carefully considered. So, the performance of chip is limited under 5bit. With these problem, the noise analysis and evolve way will be discussed in the thesis.

並列關鍵字

pipeline ADC ； time domain ； comparator ； overshoot ； noise

參考文獻

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