使用多重電壓之低功率高階合成方法

可攜式消費電子市場經常需要較強大功能、較小、較輕及較長電池壽命的產品。在以電池為主要供電來源的手持式系統中，低耗電的設計需求遽速上升，主要的原因是降低能量消耗能夠讓此類設備使用時間延長。既便是在高階電腦系統中，低功率仍是一個重要的設計考量，因為昂貴的冷卻、包裝成本以及低可靠度常與大量功率消耗有關。高階合成(high-level synthesis)包含排程(scheduling)、連結(binding)、與分配(allocation)，在本論文中，我們主要著重於多重電壓排程方法，因為多重電壓技術在低功率設計領域中是一項相當有用的方法。多重電壓排程指的是配置一個合適的電壓給控制資料流程圖(CDFG)中的每個節點，以便於整個系統在給定的時間限制下，降低其功率消耗。在本篇論文中，我們提出了兩個多電壓排程方法：多重供應電壓(multiple supply voltage)排程以及雙供應電壓雙臨界電壓(dual supply voltage and dual threshold voltage)排程。不同於以往的研究總是將焦點集中在臨界路徑上，並利用鬆弛時間(slack time)來調整其他非臨界節點的電壓，使用本論文所提出的方法能夠處理所有的節點而不需考慮臨界路徑的問題，優點是可以讓電壓配置更具有彈性。在多重供應電壓排程中，我們分析並比較多重電壓對高階合成的影響，而在雙供應電壓雙臨界電壓排程中，我們不但考慮動態功率消耗，也同時將靜態功率消耗列入考量。此外，我們也提出了一個結合基因演算法與模擬退火法的特殊演算法來解決高階雙電壓排程問題。

關鍵字

低功率；高階合成；多重電壓；排程

並列摘要

The portable consumer electronics market is constantly demanding more powerful capabilities, smaller and lighter products, and longer battery life. Demand has risen sharply for low power consumption in battery-powered hand-held systems owing to the key requirement to reduce power dissipation to extend service. Even in high-end computer systems, low power is still a critical design consideration, since the expensive cooling and packaging costs and lower reliability associated with high-level on-chip power dissipation are significant. High-level synthesis consists of scheduling, binding and allocation, and in this dissertation the main focus falls on the multiple voltages scheduling aspect. The multiple voltage technique is one of several useful techniques in the low power design field. The multiple voltage scheduling refers to the assignment of a voltage level to each operational node in a data flow graph to minimize the total power consumption within a given computation time. In this dissertation, we propose two multiple voltage scheduling methods: multiple supply voltage (MSV) scheduling and dual supply voltage and dual threshold voltage (DSDT) scheduling. Unlike previous research, which focused on the operational nodes in the critical path and used the slack time to change the voltage of other nodes, our methods deal with all nodes without considering whether a node is in the critical path, our method deals with all nodes without considering whether a node is in the critical path. The advantage of this method is that the voltage assignment becomes very flexible. In the MSV scheduling, we analyze and compare the multiple voltage effect on high-level synthesis, and in DSDT scheduling, we take into account not only the dynamic power but also the static power consumption. Besides, a special algorithm which combines genetic algorithm and simulated annealing algorithm is proposed to solve the high-level dual-voltage scheduling problem.

並列關鍵字

low power ； high-level synthesis ； multiple voltage ； scheduling

參考文獻

[24] J. M. Chang, and M. Pedram, Power Optimization and Synthesis at Behavioral and System Levels. Kluwer Academic Publishers, Boston, 1999.

[32] K. L. Tsai, S. W. Chang, F. Lai, and S. J. Ruan, “A low power scheduling method using dual Vdd and dual Vth,” in IEEE Proc. of Int'l Symp. on Circuits and Systems, pp. 684—687, May 2005.

[1] U.S. Environmental Protection Agency (EPA) http://epa.gov/

[3] P. Pant, R. K. Roy, A. Chattejee, “Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 9, Issue 2, pp. 390—394, Apr. 2001.

[6] A. R. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design. Kluwer Academic Publishers, Norwell, MA, 1995.

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使用多重電壓之低功率高階合成方法

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