掃描測試時降低電力消耗之多重輸入控制樣本產生器

隨著超大型體電路技術(VLSI technology)的進步，高效能、低成本以及高密度的晶片已經成為主流，因此晶片測試的難度也越來越高，降低測試期間的功率消耗也變得越來越重要。尤其在掃描測試的架構(scan-based architecture)下，測試資料移位(shift)至掃描細胞(scan cell)期間會造成過多的功率消耗，而測試期間過多的功率消耗會導致電路成本增加以及良率的降低。因此，減小在掃描測試(scan test)期間，測試資料移位(shift)至掃描細胞的功率消耗將可以避免上述問題的產生。本篇論文中，我們依據每個實際測試向量(test vector)計算出掃描細胞(scan cell)的信號轉變機率(signal probability)及電路中各個邏輯閘的轉變密度(transition density)，並使用一個轉變衝擊方程式(impact function)來測量每一個邏輯閘在測試期間對受測電路造成的影響，再依據此影響程度，設計一個演算法得到多個用在主要輸入端(primary input)的控制樣本(control pattern) 。這個控制樣本(control pattern) 可以在掃描測試的掃描細胞資料移位(shift)時盡最大可能來阻止0-1轉換(transition)的繁衍，達到有效地降低功率消耗就如同減少0-1轉換次數一樣。最後，可以由實驗結果觀察到，我們提出的方法能夠在沒有違反佈局限制條件下，有效地降低測試期間的功率消耗。實驗結果並顯示出本篇論文所提出的方法在0-1轉換, 也就是功率消耗(power dissipation)上可達到38.46%的改善程度。這結果均優於單一控制樣本的主要輸入端控制樣本PIBP (Primary Input Blocking Pattern)及其他現有的方法。

關鍵字

大型積體電路；掃描測試；轉變密度；電力消耗；主要輸入端；轉變衝擊方程式

並列摘要

As the VLSI technology grows up, high performance, low-cost, high density integrated circuits became main stream. Hence, testing for integrated circuit is more and more complex and reducing the power consumption during testing is also more and more important. Especially, in the scan-based testing, the spurious transitions will be produced by scan flip-flops during shift cycles and the spurious transition will dissipate more power and lead to loss of yield or decrease the reliability of the circuit under test. Therefore, minimize the power consumption of full-scan circuits during shift cycles can avoid the above problem. In this thesis, we calculate the signal probability of all scan cells and transition density of all gates for each test vector. We also calculate the influence degree of each gate with impact function value. The impact function value is used to estimate whether a gate has high influence or low influence in the circuit. According to the influence of each gate, we propose a new algorithm to generate a blocking pattern for each test vector, it is applied to the primary inputs during shift cycle and can block the switching activity which occurs in the combinational part of the circuit as many as possible during test, and can efficiently reduce the power consumption as same as transition count. Finally, the experimental results on the ISCAS 89 benchmark circuits show that our proposed approach can achieve 38.46% improvement efficiency for most circuits and always produces better results than PIBP and existing approaches.

並列關鍵字

VLSI ； scan based circuit ； spurious transition ； power dissipation ； primary input ； impact function

參考文獻

[1] P. Girard, “Survey of low-power testing of VLSI circuits,” IEEE Design & Test of Computer, vol. 17, Issue 3, pp. 80-90, May 2002.

[2] Bonhomme, Y, Girard, P, Landrault, C, Pravossoudovitch, S, “Test power: a big issue in large SOC designs” Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on 29-31 Jan. 2002 Page(s):447 – 449.

[3] Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” Proc. 11th IEEE VLSI Test Symp., 1993, pp. 4-9.

[4] V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. Reddy, “Techniques for minimizing power dissipation in scan and combinational circuits during test application,” IEEE Trans. Computer-Aided Design, vol. 17, pp. 1325-1333, Dec. 1998.

[5] S. Gerstendorfer and H. J. Wunderlich, “Minimized power consumption for scan-based BIST,” Proc. IEEE int’l Test Conf., 1999, pp. 77-84.

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掃描測試時降低電力消耗之多重輸入控制樣本產生器

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