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  • 學位論文

新式的掃描測試方案以降低移動功率消耗

A New Scan Scheme for Shifting Power Reduction

指導教授 : 饒建奇

摘要


本篇論文提出一種修改掃描鏈的方法,目的在於減少移動功率的消耗。利用本篇論文所提出的演算法不需要修改測試資料以及測試資料移入的順序,在掃描測試期間可以專注於降低移出功率的消耗。所提出的演算法步驟主要在於指定Response至合適的移出掃描鏈順序中,以降低測試資料在移出掃描鏈時的切換頻率。我們利用增加一個額外的控制訊號去切換掃描鏈的移入及移出模式。為了驗證所提出方法的有效性,我們實驗在ISCAS’89的六個大型測試基準電路上,實驗結果顯示,我們所提出的方法能有效地降低移動功率的消耗。

關鍵字

掃描測試 低功率

並列摘要


This paper presents a scan chain modification scheme aiming at minimizing scan-shift power in this paper. We focus on reducing the scan-out power during scan shift when using our algorithm without modification of test patterns and scan-in ordering. An algorithmic procedure for assigning responses in scan-out reordering reduces scan-out transitions. We only use an additional control signal to change scan-in mode and scan-out mode. To verify the effectiveness of the proposed technique, we conduct experiments on large ISCAS’89 benchmark circuits and the results show that our proposed technique significantly reduces test power consumption.

並列關鍵字

Scan Testing Low Power

參考文獻


[1] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,” in Proc. IEEE VLSI Test Symp. (VTS’93), Atlantic City, NJ, USA, Apr. 6-8, 1993, pp. 4-9.
[2] P. Girad, “Survey of Low-Power Testing of VLSI Circuits,” IEEE Design & Test of Computers, vol. 19, no. 3, May/June, 2002, pp. 82-92.
[4] K. J. Lee, T. C. Huang, and J. J. Chen, “Peak-power reduction for multiple-scan circuits during test application,” in Proc. IEEE Asian Test Symp. (ATS’00), Taipei, Taiwan, Dec. 4-6, 2000, pp.453-458.
[5] S. Wang and S. K. Gupta, “ATPG for Heat Dissipation Minimization during Test Application,” IEEE Trans. Computers, vol. 47, no. 2, Feb. 1998, pp. 256-262.
[6] S. Wang and S. K. Gupta, “ATPG for Heat Dissipation Minimization for Scan Testing,” in Proc. ACM/IEEE Design Auto. Conf. (DAC’97), New York, NY, USA, 1997, pp. 614-619.

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