This paper presents a scan chain modification scheme aiming at minimizing scan-shift power in this paper. We focus on reducing the scan-out power during scan shift when using our algorithm without modification of test patterns and scan-in ordering. An algorithmic procedure for assigning responses in scan-out reordering reduces scan-out transitions. We only use an additional control signal to change scan-in mode and scan-out mode. To verify the effectiveness of the proposed technique, we conduct experiments on large ISCAS’89 benchmark circuits and the results show that our proposed technique significantly reduces test power consumption.