新穎且有建設性的資料壓縮方案應用於低功耗測試

隨著超大型積體電路(very large scale integration, VLSI)的設計趨勢演變成系統單晶片(system-on-a-chip, SoC)設計，一顆系統晶片包含了許多可重複使用的矽智財(intellectual property, IP)。為了能夠完整地測試所設計的電路，我們必須事先產生測試時所需要的測試資料，並且將這些測試資料儲存在自動測試機台(automatic test equipment, ATE)的記憶體中。可想而知的是，隨著積體電路(integrated circuit, IC)越來越複雜，測試資料量是非常龐大的，而自動測試機台的通道頻寬與記憶體容量是有限的。如此一來，要將龐大的資料量從自動測試機台的記憶體中透過有限頻寬的通道來傳送到待測電路是有困難的。針對這個問題，測試資料壓縮(test data compression)技術是一個常用的解決方法。這主要的效益不僅能夠減少資料量，更能夠同時達到縮短測試應用時間的效果。在本篇論文中，我們提出兩個測試資料壓縮方案應用於低功耗測試。在第3章中，我們提出一種低功耗的測試資料壓縮技術，其適用於單一掃描鏈的架構。在本方法中，我們提出一個掃描鏈重新排列的演算法來降低測試功率消耗。此外，我們還提出了一種測試片段差異(test slice difference, TSD)的技術，以減少測試資料量。此技術在硬體的實現上只需要單一個掃描元件(scan cell)。因此，與環狀的掃描鏈(cyclical scan chains, CSR)技術比較，我們所提出的方法具有較高的實用價值。從ISCAS’89測試電路的實驗結果中可以看出，我們所提出的方法能夠得到較高的資料壓縮率。與其它有名的測試資料壓縮技術比較，在測試功率消耗的部分，亦能獲得較佳的結果。在第4章中，針對多重掃描鏈的測試環境，我們提出一種新穎且有建設性的資料壓縮方案來降低測試資料量，並節省測試時的功率消耗。我們的方法只儲存資料的轉換點資訊於自動測試機台中。並且利用“Read Selector”硬體來過濾掉不需要編碼的資料。本方法的解壓縮器硬體使用緩衝器(buffer)來暫存上一筆資料的狀態。我們還提出一個重新配置多重掃描鏈的演算法，並且提出一個新式的線性相依(linear dependency)計算方法來找出隱蔽的線性相依關係。在測試實例部分，我們使用ISCAS’89測試電路來模擬。在實驗結果中顯示，我們所提出的方法優於selective scan slice encoding。其壓縮率與功率消耗分別改善了57%與77%。

關鍵字

測試資料壓縮；低功耗測試；可測試設計

並列摘要

As the design trends of very large scale integration (VLSI) circuit evolve into system-on-a-chip (SoC) design, each chip contains several reusable intellectual property (IP) cores. In order to test the chip completely, we must generate a test set for testing in advance, and store these test patterns in memory of automatic test equipment (ATE). One can imagine that test data volume increases as the integrated circuits (ICs) become complex, yet the bandwidth and memory capacity of ATE is limited. Thus, it is difficult to transmit huge test data from ATE memory to SoC. Test data compression is one of the most often used methods to deal with this problem. This technique not only reduces the volume of test data, but also shortens test application time simultaneously. In this thesis, we present two test data compression scheme for low-power testing. In Chapter 3, a low power strategy for test data compression scheme with single scan chain is presented. In this method, we propose an efficient algorithm for scan chain reordering to deal with the power dissipation problem. In addition, we also propose a test slice difference (TSD) technique to improve test data compression. It is an efficient technique and only needs one scan cell. Consequently, hardware overhead is much lower than the cyclical scan chains (CSR) technique. In experimental results, our technique achieves high compression ratio for several large ISCAS’89 benchmark circuits. The power consumption is also better compared with other well-known compression technique. In Chapter 4, we present a novel constructive data compression scheme that reduces both test data volume and shifting-in power for multiple scan chains. In this scheme, we only store the changed point information in ATE and use “Read Selector” to filter unnecessary encoded data. The decompression architecture contains buffers to hold the preceding data. We also propose a new algorithm to assign multiple scan chains and a new linear dependency computation method to find the hidden dependency between test slices. Experimental results show that the proposed scheme respectively outperforms previous method (selective scan slice encoding) by 57% and 77% in test data volume and power consumption on larger circuits in ISCAS’89 benchmarks.

並列關鍵字

Test Data Compression ； Low Power Testing ； Design for Testability(DFT)

參考文獻

[1] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing, Norwell, MA: Kluwer, 2000.

[2] The International Technology Roadmap for Semiconductors (ITRS): 2007 Edition. http://www.itrs.net/Links/2007ITRS/Home2007.htm.

[3] Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” in Proc. IEEE VLSI Test Symp. (VTS’93), Atlantic City, NJ, USA, Apr. 6-8, 1993, pp. 4-9.

[4] P. Girad, “Survey of low-power testing of VLSI circuits,” IEEE Design & Test of Computers, vol. 19, no. 3, May-June, 2002, pp. 82-92.

[5] A. Jas and N. A. Touba, “Test vector decompression via cyclical scan chains and its application to testing core-based designs,” in Proc. IEEE Int. Test Conf. (ITC’98), Washington, DC, USA , Oct. 18-23, 1998, pp. 458-464.

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新穎且有建設性的資料壓縮方案應用於低功耗測試

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