降低掃描鏈測試功率之自動測試圖樣產生技術

A Low Power Test Pattern Generation Methodology for Scan Testing

胡凱舜(Kai-Shun Hu)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.02155

摘要

平均與最高功率管理在現行掃描鏈測試中成為一個嚴重的議題，測試IC時會產生比一般工作情況下更大的功率消耗，本篇論文提出一個新的自動測試圖樣產生技術，目標在降低測試功率消耗，此技術同時考慮移入(shift)與捕捉(capture)時之平均與最高功率消耗。 此技術整合一功率限制之自動測試圖樣產生引擎，一功率限制之動態測試向量壓縮機制，一未指定值位元填充(X-filling)方法，與一重新安排測試向量順序方法，以達到降低功率之目的。此外，本論文提出一機制，將此降低測試功率技術與現行商業自動測試圖樣產生器連接，用以降低此降低測試功率技術所需之執行時間但仍保有相同之降低功率效能。此技術可應用在不同故障模型(fault model)與不同測試條件中，實驗中使用ISCAS89電路驗證此技術於不同故障模型中皆有效降低平均與最高功率消耗。

關鍵字

掃描鏈 ； 功率 ； 自動測試圖樣產生

並列摘要

Average and peak power management has become a serious challenge for scan-based testing. This thesis proposes a test pattern generation methodology that reduces the power dissipation during the shift and capture cycles of conventional scan testing. The proposed methodology utilizes a power-constrained ATPG engine and a dynamic compaction scheme to generate partially specified low power patterns. Then, X-filling together with test pattern ordering is employed to enhance the achievable power reduction. Besides, a mechanism of integration with commercial ATPG is proposed which iteratively replaces the high power consumption patterns with low power ones. Furthermore, the proposed low power test pattern generation methodology can be extent to various fault models, different test application scheme, and different test application conditions. The proposed technique is validated using ISCAS89 benchmark circuits.

並列關鍵字

scan chain ； low power ； ATPG

參考文獻

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[Bonhomme02] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “Power Driven Chaining of Flip-flops in Scan Architectures,” International Test Conference, 2002, pp. 796-803.

[Bonhomme03] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint,” International Test Conference, 2003, pp. 488-493.

[Butler04] K. M. Butler, J. Saxena, T. Fryars, and G. Hetherington, “Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques,” International Test Conference, 2004, pp. 355-364.