在多掃描鏈電路下重新安排掃描細胞達到減少測試時間與能量消耗

由於現今IC製程技術的進步，讓我們可以設計出更精密複雜的電路。但同時當我們在測試IC時也會產生兩個問題：首先，是功率消耗的問題。因為當我們在測試IC時會產生比一般工作情況下更大的功率消耗。再者，就是將測試資料(test vector)輸入(shift into)到掃描鏈(scan chain)時，需要耗費大量的時間。而為了解決測試時所花費的時間，我們提出了一個不需要額外增加硬體的掃描測試架構(scan-based architecture)。一般而言，在全掃描電路中，測試資料內會含有大量的未指定值位元(don't-cares bit)，在大多測試資料中會有超過百分之八十以上的未指定值位元（在IBM的報告中，有些電路的測試資料中未指定值的位元更會高達百分之九十八），因此，我們可以知道在測試資料中已指定值的位元個數是非常稀少的，而針對那些未指定值的位元，我們可以任意的指定其值為1或0，如此便可以減少輸入到掃描串列的測試資料量。而除了未指定值的位元個數的因素外，還有一點要觀察的就是測試回應(test response)的值，這兩種因素都是影響到最後結果是好或壞的關鍵。我們也會根據每個掃描細胞中輸入資料(測試資料)內已指定值位元的個數與輸出資料(測試回應)內的已指定值位元的個數比例，對掃描細胞(scan cell)重新排序。而我們排序的原則就是，盡量讓測試資料所需要移出的輸出時脈個數，盡可能等於下一組測試資料所需移入的時脈個數。最後我們還需要重新排序測試資料的順序，藉此達到減少最多的測試時間與能量消耗。

關鍵字

多掃瞄鏈；掃描細胞；重新排序；未指定位元

並列摘要

When the process of very large-scale integrated circuits scales down into deep sub-micron, the complexity of circuit designs is greatly increased. So, there are two problems in the IC (Integrated Circuit) testing: First, the circuit in test mode consumes more power than in normal mode. Second, shifting test vectors into the scan chain is a time consuming process. To solve these problems, we propose a scan cell ordering approach to reduce test power as well as testing time. Generally, there are a large number of don't-cares (unspecified bit or X’ bit) in the test vectors for full scan circuits, sometimes the test vectors are more than 80% ( IBM has ever reported that for some of their designs about 98% of the bits in test patterns are don't care bits ). Thus it brings the sparseness of specified bits in test vectors and the freedom to assign these don't-cares with arbitrary values. By ordering the don’t care bits we can reduce the test volume shifted into scan chain. Besides, we reorder the scan chain by arranging the scan cells with high ratio of test vector care bits and the response care bits in the beginning of scan chain and the cell with low ratio in the tail of the scan chain.

並列關鍵字

multi-scan circuits ； scan cell ； reordering

參考文獻

[1] Y. Zorian, “A Distributed BIST Control Scheme for Complex VLSI Devices,”in Proc. VLSI Test Symp. (VTS’93), pp.4-9, 1993.

[3] Ozgur Sinaoglu and Alex Orailoglu (San Diego University) “A Novel Scan Architecture for Power-Efficient, Rapid Test” Computer Aided Design, 2002.

[6] Sying-Jyan Wang; Sheng-Nan Chiou; “Generating Efficient Tests for Continuous Scan” Design Automation Conference, 2001. Proceedings 2001 Page(s):162 - 165

[7] Sankaralingam, R.; Pouya, B.; Touba, N.A.; “Reducing Power Dissipation During Test Using Scan Chain Disable” VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001 29 April-3 May 2001 Page(s):319 - 324 Digital Object dentifier

[9] C. Su and K. Huang, “A serial scan test vector compression methodology,” in Proc. Intl. Test Con$, pp. 981-988, 1993.

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在多掃描鏈電路下重新安排掃描細胞達到減少測試時間與能量消耗

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