應用於Serial-ATA之6GHz低相位抖動展頻時脈產生器之設計與實作

Design and Implementation of a Low-Jitter 6GHz Spread Spectrum Clock Generator for Serial-ATA

張呈毓(Cheng-Yu Chang)

指導教授 ： 陳少傑

共同指導教授 ： 張棋(Chi Chang)

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.10449

摘要

無資料

關鍵字

展頻時脈 ； 展頻時脈產生器 ； 鎖相迴路 ； 除小數式 ； 三角積分調變器 ； 電磁干擾 ； 相位抖動 ； 小數突波 ； 壓控振盪器

並列摘要

EMI (Electro-Magnetic Interference) causes more destruction to the transmitting signal since the operating frequency is higher than before. Spread spectrum clocking (SSC) is a method that can reduce the EMI effectively. This method is more and more popular since it is easy to design and suitable for integrated IC. Serial ATA is a high speed external mass storage device having the SSC specifications as following: a triangular modulation profile with down spread, a 5000 ppm frequency deviation, a 30~33KHz modulation frequency, an EMI reduction larger than 7dB, and a 3ps RMS jitter @ 250 cycles.
Our research is stressed on low-jitter design. Due to the higher operating frequency requirement, design with low-jitter performance becomes more and more important and thus more difficult to realize. VCO phase noise dominates the jitter performance of PLLs. Therefore, we proposed a LC tank VCO with low phase noise characteristic. The simulation results show that the phase noise is -119.8dBc/Hz @1MHz offset voltage and FoM is -190.8.
In this Thesis, a spread spectrum clock generator (SSCG) modulated by a divider is presented. The PLL is fabricated in a 0.18μm CMOS process and the whole SSCG system is integrated and tested on an FPGA board. The simulation results show that all specifications of the Serial ATA have been achieved in our system and the jitter measurement shows that the RMS jitter is 0.4ps @ 250 cycles.

並列關鍵字

SSC ； SSCG ； Serial ATA ； PLL ； Fractional-N ； Δ-Σ modulator ； EMI ； Jitter ； Fractional spurs ； Voltage Controlled Oscillator

參考文獻

[2] K.B. Hardin, J.T. Fessler, and D.R. Bush, “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions,” IEEE International Symposium on Electromagnetic Compatibility, pp. 227–231, Aug. 1994.

[5] H.W. Chen and J.C. Wu, “A Spread Spectrum Clock Generator for EMI Reduction,” IEICE Trans. Electron., vol. E84-C, no. 12, pp. 1959-1966, Dec. 2001.

[6] Y. Moon, D.K. Jeong, and G. Kim, “Clock Dithering for Electromag Netic Compliance Using Spread-Spectrum Phase Modulation,” IEEE International Solid-State Circuits Conference, pp. 186–187, Feb. 1999.

[7] M. Aoyama, K. Ogasawara, M. Sugawara, T. Ishibashi, S. Shimoyama, K. Yamaguchi, and T. Yanagita, “3Gbps, 5000ppm Spread Spectrum SerDes PHY with Frequency Tracking Phase Interpolator for Serial ATA,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 107-110, Jun. 2003.

[8] J.Y. Michel and C. Neron, “A Frequency Modulated PLL for EMI Reduction in Embedded Application,” IEEE International ASIC/SOC Conference, pp. 362–365, Sep. 1999.