應用於3GHz以下無線諧波抑制接收機之互補式金氧半場效電晶體電路與系統架構設計

CMOS Circuits and Architecture Design Techniques for Sub-3GHz Wireless Harmonic Rejection Receiver

李華錦(Hua-Chin Lee)

指導教授 ： 汪重光

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2011年)

https://doi.org/10.6342/NTU.2011.10123

摘要

本論文主要著重在研究與分析諧波抑制之原理應用在寬頻感知無線電系統接收機。傳統分析諧波抑制之方式是使用向量分析的方式，進而討論在抑制第三諧波與第五諧波電路設計上面的技巧。由於諧波抑制之原理與數位電路中的有限脈衝響應濾波器原理近似，且有相同之處，因此，在本論文中先由數位有限脈衝響應濾波器抑制諧波原理推導出數學模型，進而利用數位類比之數學模型將原有離散時間模型公式轉換成連續時間模型公式；利用轉換出之公式可以推導出相對應之電路系統架構，也因此可以更為清楚瞭且證明諧波抑制的原理。除此外，可以更為清楚瞭解諧波抑制之優缺點，以便在電路設計時能更嚴謹地設計出出色之具有諧波抑制之接收機。

本論文提出精確之數學推導方式證明傳統以向量解釋之諧波抑制系統，也因此，更能精準預測在電路上之不匹配所造成在諧波抑制上的影響；除此外，也提出一個具有雜訊抑制架構之射頻前端低雜訊放大器，使得所設計之感知無線電系統接收機在功耗、效能都能比以往的接收機來得好。以此數學模型設計出之感知無線電系統接收機能操作在0.1-1.2GHz頻段，並具有4dB雜訊係數，並將射頻前端低雜訊放大器、混波器、頻率合成器與諧波抑制濾波器全部整合在同一晶片當中。

論文之創新性：1. 本論文提出以數學模型之方式分析諧波抑制電路；2. 利用數學模型轉換出精確之相對應電路；3. 提出具有雜訊抑制之射頻前端低雜訊放大器設計

關鍵字

感知無線電 ； 諧波抑制 ； 電視頻段 ； 低雜訊放大器 ； 混波器 ； 頻率合成器與濾波器

並列摘要

Modern wireless data communication has been in the demand for various applications and di¤erent wireless communication standards. In order to increase data rate for data transmission, choice of utilizing wide bandwidth is much easier than enhancing channel capacity through the signal-to-noise ratio. Therefore, exploring new techniques to use wide bandwidth plays an important role in the future wireless communication systems.
However, to e¢ ciently use the desired frequency spectrum, the cognitive radio (CR) systems are proposed to solve this issue. This system has capability to sense the environment variances, and dynamically adjusts its bandwidth, modulation, power, and other parameters, in order to achieve optimal performances and maximum transmission rate. The dissertation takes the cognitive radio system on TV bands and UNII bands as the reference to discuss the circuits and architecture design of the wideband wireless receiver.
A wideband direct-conversion (DC) harmonic-rejection (HR) receiver front-end with built-in switched-load PLL-based frequency synthesizer is proposed and validated with measurements for cognitive radio standard and systems. The direct-conversion harmonic-rejection (DCHR) receiver consists of a broadband gm-boosted high dynamic range noise-cancelling low-noise ampli.er (LNA), an 8-phase switching mixer array, a two-stage cascaded HR low-pass filter and an 8-phase switched-load PLL-based frequency synthesizer. Realized in a 90-nm 1P9M digital CMOS technology with an active area of 1x1 mm2, the DCHR receiver achieves a 34 dB conversion gain, 50 dB and 53 dB of 3rd and 5th harmonic rejection respectively without any o¤-chip RF filtering. The measured minimum receiver noise .gure (NF) is 3:5 dB, and the average measured NF is 4 dB within the entire 3 dB bandwidth. Furthermore, the IIP3 is -10 dBm from 100MHz to 1:2 GHz with 5MHz tone spacing. The total power consumption is 28:6mW with embedded LNA, switching mixer, HR low-pass filter and frequency synthesizer under 1 V supply operation.

並列關鍵字

Cognitive radio ； harmonic rejection ； low-noise ampli…er ； mixer ； frequency synthesizer ； filter

參考文獻

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[4] IEEE Spectrum: The End of Spectrum Scarcity (http://www.spectrum.ieee.org/mar04/3811)

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