直接降頻接收機之偶階諧波頻率混合器設計與分析

在無線通訊系統高度發展的現在，雖然多數電路陸陸續續的數位化，但在數位的周邊類比以及高頻電路卻依然是不可或缺的一個區塊，其效能影響對後面數位電路的影響也甚為重大，在數位電路的最前線亦即所謂的前端(front-end)電路在前端(front-end)的架構中，天線接收端的信號經過第一及低雜訊放大器(LNA)的放大以後，隨即需要的即是頻率混合器 (Mixer)，降頻到零頻(ZeroIF)以後以傳給之後的類比數位轉換器(ADC)使用，因此在頻率混合器電路的設計中首重電路本身的線性度，再來則為功率散逸，最後才是轉換增益(conversion gain)的考量，而在直接降頻的架構中，因為要避免壓控震盪器(VCO)所構成的震盪器漏失(LO leakage)而造成的直流偏異(DC offset)近年來利用偶階諧波來混頻的技術便普及於頻率混合器的電路架構中，即是利用訊號的偶階諧波項次(even-harmonic term)來與高頻的訊號相混頻。但是雖然偶階諧波頻率混合器可以有效的解決直接降頻最在意的直流偏異的問題，但在設計上卻也有其困難性，包括了偶階諧波較小所造成的轉換增益過低的問題，因此需要較大的功率散逸以及較高的電壓偏壓方能維持轉換增益在要求的範圍內。在CMOS製程不斷進步的現在偏壓可以不斷的下降，若配合電路的技巧，更可以降低電量以及能量的使用。此篇論文提出了一個新的偶階諧波混頻器的架構以降低整體的功率散逸以及供給電壓，此設計以線性度以及功率散逸為首要考量，試圖將這兩項特性最佳化，並且維持其他的特性在合理的範圍值內，所用的方法為將疊接的架構改完串接，詳細內容將在論文內完整討論。共提出四個不同的電路分別為兩個寬頻MIXER設計、一個單頻MIXER以及一個被動MIXER電路，寬頻MIXER在低功率的情況下做到了增益平坦，單頻則在極小的功率散逸內達到了相當不錯的效能，以及被動電路改進了ㄧ般傳統的被動電路的缺點，並且達成到一個很小的轉換工率增益(Conversion Power Gain).

關鍵字

偶階諧波；頻率混合器

並列摘要

Wireless Communication System has been highly developed for quite a long time. Although many circuits are operating in digital format nowadays, analog and radio frequency circuits are still important blocks in the system. Because digital circuits take signal from radio-frequency IC, digital circuits are highly affected by the surrounding circuits which are so-called the front-end architecture. In receiver, antenna receives signal from the air. Signal was amplified by the LNA which is the first stage of the front-end. After LNA, signal needs to be down-converted to base-band which is done by mixer. Mixer designers concentrate on linearity rather than conversion gain. Power consumption is also one of the most important specifications in mixer design. In order to avoid DC offset which is caused by LO self-mixing, even-harmonic topology is developed in recent years. That is, use second order harmonic frequency term of local-oscillator to accomplish the frequency mixing. Although even harmonic topology efficiently reduces DC offset issue, it also has its own design difficulties such as higher power consumption and higher supply voltage. High power is needed to enhance conversion gain. Since CMOS technology is constantly developed in order to reduce supply voltage, circuits design skills need to be developed with process improvement to decrease energy dissipation. In this thesis, a novel technique to reduce power dissipation and supply voltage is presented. This design focuses on linearity and power consumption of the circuit, and maintains the other characteristics in reasonable values. Cascoding topology is used to achieve this goal in stead of cascading. Four different circuits are designed, including two broad-band mixers, one narrow-band mixer and one passive mixer. Improved Broad-band mixer achieves flat conversion gain with fairly small power consumption. Narrow-band mixer also has very good characteristics and consumes relatively low power. Passive one solves the problems of the conventional anti-parallel diodes in terms of LO and RF signal combination issue. Loss of the mixer is only 3 dB power which is also a prominent characteristic.

並列關鍵字

Even ； Harmonic ； Mixers

參考文獻

[1] B. Razavi, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits and Systems II, vol. 44, no. 6, pp. 428-435, June 1997.

[2] Baltus, P.G.M., Dekker, R., “Optimizing RF front ends for low power” IEEE Trans. Circuits and Systems, Page(s):1546 – 1559, Oct. 2000

[3] Simon, M.K., “On the bit-error probability of differentially encoded QPSK and offset QPSK in the presence of carrier synchronization”, Communications, IEEE Transactions, Page(s):806 – 812, May 2006.

[4] Li, Q. and Yuan, J.S. , “Linearity analysis and design optimisation for 0.18 μm CMOS RF mixer” Circuits Devices and Systems IEEE Proceedings , Page(s):112 – 118, April 2002.

[5] Amrouche, F., Allam, R., Paillot, J.M., “Simulation and analytical calculation of the noise figure in HEMT gate mixers” Microwave Conference, 2003. 33rd European, Page(s):351 – 354, Oct. 2003

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直接降頻接收機之偶階諧波頻率混合器設計與分析

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