機率電路測試圖樣壓縮

Test Pattern Compression for Probabilistic Circuit

張志銘(Chih-Ming Chang)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201702295

摘要

無資料

關鍵字

機率電路 ； 測試樣型壓縮 ； 錯誤模型

並列摘要

Probabilistic circuits are very attractive for the next generation ultra-low power designs. It is important to test probabilistic circuits because a defect in probabilistic circuit may increase the erroneous probability. However, there is no suitable fault model and test generation/compression technique for probabilistic circuits yet. In this paper, a probabilistic fault model is proposed for probabilistic circuits. The number of faults is linear to the gate count. A statistical method is proposed to calculate the repetition needed for each test pattern. An integer linear programming (ILP) method is presented to minimize total test length, while keeping the same fault coverage. Experiments on ISCAS’89 benchmark circuits show the total test length of our proposed ILP method is 2.77 times shorter than a greedy method.

並列關鍵字

Probabilistic Circuit ； Test Pattern Compression ； Fault Model

參考文獻

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