機率電路測試圖樣生產與壓縮

ATPG and Test Compression for Probabilistic Circuits

楊凱傑(Kai-Chieh Yang)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201803109

摘要

因為次世代極低功耗電路設計以及量子電腦的發展，機率電路可說是日益重要。不像傳統電路，測試圖樣只需測試一次，測試機率電路時，同一個測試圖樣需要測試數次，藉此估算錯機率。然而，過去技術都有著很長的測試圖樣長度，這導致電路測試的時間也隨之變長。在本篇論文中，我們提出一個機率電路測試圖樣生產演算法。我們用特殊的機率錯誤激活以及機率錯誤傳遞方法來減少我們測試圖樣重複的次數。我們同時也提出將不同測試圖樣貢獻累積的技術，藉此更進一步減少測試圖樣長度。實驗顯示，在ISCAS’89的電路中，我們的總測試圖樣長度比過去技術所提出的貪婪演算法平均少了34%的長度。

關鍵字

機率電路 ； 測試圖樣壓縮 ； 自動化測試圖樣生產

並列摘要

Probabilistic circuits are gaining importance in the next generation ultra low-power computing and quantum computing. Unlike testing deterministic circuits, where each test pattern is applied only once, testing probabilistic circuits requires multiple pattern repetitions for each test pattern. However, previous test pattern selection techniques require long test length so it is time consuming. In this thesis, we propose an ATPG algorithm for probabilistic circuits. We use specialized activation and propagation methods to reduce pattern repetitions. Also, we propose to accumulate contribution among different patterns to further reduce pattern repetitions. Experiments on ISCAS’89 benchmark circuits show the total test length of our proposed method is 34% shorter than a greedy method [Chang 17].

並列關鍵字

Probabilistic Circuit ； Test Pattern Compression ； ATPG

參考文獻

[Breuer 05] M. A. Breuer. "Multi-media applications and imprecise computation," Digital System Design, 2005. Proceedings. 8th Euromicro Conference on. IEEE, 2005.

[Chang 17] C. M. Chang, K. C. Yang, J. C. M. Li, and H. Chang. "Test Pattern Compression for Probabilistic Circuits," Asian Test Symposium, 2017.

[Cheemalavagu 05] S. Cheemalavagu, P. Korkmaz, K. V. Palem, B. E. S. Akgul, and L. N. Chakrapani. "A probabilistic CMOS switch and its realization by exploiting noise, " IFIP International Conference on VLSI, 2005.

[Han 05] J. Han, E. Taylor, J. Gao, and J. Fortes. "Faults, error bounds and reliability of nanoelectronic circuits," International Conference on Application-Specific Systems, 2005.

[Han 11] J. Han, H. Chen, E. Boykin, and J. Fortes. "Reliability evaluation of logic circuits using probabilistic gate models," Microelectronics Reliability, 2011.