RLC時脈繞線之串音分析與減少

Crosstalk Analysis and Reduction for RLC-Based Clock Routings

高健文(Chien-Wen Kao)

指導教授 ： 蔡加春

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2005年)

摘要

在高效能晶片或是系統晶片(SoC)中的多重時脈(Multiple clock)相互之間產生的串音(Crosstalk)是不能被忽略，因為串音干擾會讓電路產生延遲，而使電路效能下降，嚴重的情況還可能造成電路無法正常工作，所以如何有效的降低串音干擾是目前很重要的問題。
在本論文中我們首先分析兩個RLC時脈繞線相互之間的串音有耦合電容與互感及其對時脈延遲(Clock delay)與時脈傾斜誤差(Clock skew)的影響，測試結果在0.13微米製程之下發現，(a)因為長線段時脈阻尼因數總是大於1，以至於不同頻率對時脈延遲影響很小，(b)當兩平行線段距離大於23um，使得在每單位長度延遲少於0.0107ps或3%以下，故可忽略其相互之間的串音，(c)在兩個時脈繞線中有相互間的串音使其時脈延遲與傾斜誤差分別增加19.1%和108.8%。接著，我們提出有效的演算法產生兩個時脈繞線同時具有串音最小化，實驗結果顯示在和無任何串音考慮下之比較，時脈延遲與傾斜誤差分別有效地下降4.4%和20%。

關鍵字

串音 ； 時脈繞線 ； 時脈延遲 ； 時脈傾斜誤差

並列摘要

The crosstalk interaction among multiple clock routings in a higher performance chip or SoC cannot be ignored. Crosstalk noise may increase the signal delay of clock routings and degenerate the system performance. A serious situation, it may cause a chip to fail. Thus, how to effectively reduce the crosstalk of clock routings is a very important problem.
In this Thesis, we first analyze the crosstalk interaction for two RLC-based clock routings with considering both coupling capacitance and mutual inductance. Running results based on 0.13

並列關鍵字

Crosstalk ； Clock routing ； Clock delay ； Clock skew

參考文獻

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