利用先進互補式金氧半電晶體製程探討在混合訊號應用中熱載子效應對匹配造成的變化

Matching Variation after HCI Stress in Advanced CMOS Technology for Mixed-Signal Application

林鴻全(Hong-Chen Lin)

指導教授 ： 黃恆盛

國立臺北科技大學/機電學院/機電整合研究所/碩士(2005年)

https://doi.org/10.6841/NTUT.2005.00205

摘要

在過去數十年，探討相同電晶體的匹配誤差研究，很多是針對與時間無關、製程上造成的變異來研究，關於可靠度分析對相同電晶體匹配誤差的研究甚少，然而它又決定電路長期使用後，功能與品質的變化。這篇論文利用由0.15μm CMOS製程所作出的不同尺寸N型跟P型電晶體，首次探討熱載子可靠度分析對匹配誤差的影響。

對類比電路電性參數來說，經過熱載子強迫後，發現N型與P型的曲線都會存在一個交叉點，基於這點，當優先考慮臨界電壓之變異時，我們找出可以使用的最小閘極面積是0.25 um2這時候的σ (△Vt,op) = 8.4 mV，或當優先考慮汲極殿留之變異時，另外一個可以使用的最小閘極面積是0.18 um2這時候的σ [(△Ids,op)/Ids,op] = 5%，對數位電路電性參數言，我們發現在汲極電流方面，匹配誤差都會獲得改善，這個現象可以用速度飽和區域遮蔽效應來解釋。總之，熱載子效應的確會造成N型電晶體匹配特性退化，但對P型電晶體卻是不明顯，因此，我們應該要進一步對每一個製程技術，或不同的製程步驟，或不同的佈局結構，估計熱載子效應對元件匹配特性的影響，以及對電路性能的影響。

關鍵字

熱載子可靠度分析 ； 不匹配 ； 匹配誤差 ； 匹配

並列摘要

Over the past few decades, a considerable number of studies have been made on the mismatches at time-independent random process-induced variations of identically designed devices in this field. Only few attempts have so far been made at the impact of stress to transistor mismatches or time-dependent mismatches of different dimensions, but the question is that the time-dependent mismatches eventually would determines circuit long-term functionality and reliability. This paper, for the first time, thoroughly presents the hot carrier stress impact on mismatch properties of n and p MOS transistors with different sizes produced using 0.15μm CMOS technology.

After HCI stress, for analog circuits’ parameters, it can be found that the after- stress lines of n and pMOSFETs exhibit cross points for both σ (△Vt,op) and σ (△Ids,op/Ids,op) drawings. Based on these cross points, it is proposed that the minimal gate area should be 0.25 um2 at σ (△Vt,op) = 8.4 mV if threshold voltage mismatch is the first priority.. And the minimal gate area should be about 0.18 um2 at σ [(△Ids,op)/Ids,op] = 5% if the drain current mismatch is to be considered first. For digital circuits’ parameters, in drain current case, the matching performance including n and pMOSFETs showed improvment after HCI stress. Velocity saturation region screen effect maybe account for this phenomenon.
To sum up, it may be desirable to mention shortly that the hot carrier injection does degrade matching of nMOSFETs’ properties. For pMOSFETs the changes are vague. Based on these observations, the HCI effects on circuit performance and reliability need to be further estimated in each technology, or different process steps, or different layout structures.

並列關鍵字

Hot Carrier Injection ； HCI ； Mismatch ； Matching

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