Research of Dynamic Analysis and Impact Life Prediction Theory for Wafer Level Package Subjected to Drop Impact

晶圓級封裝掉落衝擊動態分析及其衝擊壽命預測理論研究

周展延(Chan-Yen Chou)

指導教授 ： 江國寧

國立清華大學/工學院/動力機械工程學系/博士(2009年)

摘要

Accompanying the increasing popularity of portable and handheld products, high reliability and high resistance of drop impact capability of handheld products becomes a great concern for semiconductor and electronic product manufacturers. It is more and more important to study the dynamic response of packages during the mechanical shock caused by customer usage in portable devices and mobile applications.
In this research, the board-level drop test, failure analysis, dynamic simulation, and the theory of metal trace failure prediction under board-level drop test are established. Afterward, the structural optimal design is carried out to improve the drop test performance of packages. The stress-buffer-enhanced package with fan-out capability which can meet the high requirement of drop-test performance is applied as a test vehicle. Both drop test experiment and numerical simulation were performed. This package is provided with a thick and soft dielectric layer to absorb the impact loading to protect the solder joints. However, the meal traces within stress buffer layer suffered relatively larger deformation because of the greatly deformed dielectric layer. Fatigued metal traces in packages instead of solder joint fractures are observed to be the reason of failure during board level drop test. The fatigued trace line is the critical failure mode to be investigated in this research.
This study intends to develop a reliable impact life prediction model for metal trace which has become an imperative in estimating the performance of packages subjected to the drop impact. Through the proposed impact life prediction model, one can quantitatively determine the drop impact performance of a specified package. During the development of impact life prediction model, several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Unlike the thermal cycle test, simulation results indicate that the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Results show that the cumulative plastic strain is suitable for the impact life prediction model. The reason is that the drop test failure belongs to low cycle fatigue which is dominated by plastic strain. There is a good correlation between impact life predicted by simulations and measured by experiments. Based on the impact life prediction model, designers may execute more computational experiments in order to accelerate the time-to-market procedures.
Following, the structural design of the stress-buffer-enhanced package is accomplished. It is known that the failure mode of this package focuses on the metal trace fatigue. As a result, the trace layout design becomes an important topic in this study. In the design processes, first a proper trace layout design is recommended, and then several parametric studies are conducted to clarify the design trend and then obtain an optimal structure parameter. Finally, the structural designs, the sandwich structure, and the small chip size design, based on the stress-buffer-enhanced package are proposed to further increase the reliability under drop impact.
In this research, the theory of trace fatigue prediction under drop impact, based on the cumulative damage theory, is accomplished. Results show that the prediction model is capable to make a good estimation of drop performance. Besides, the design procedures proposed in this research are helpful on saving experimental cost and accelerating time-to-market processes.

關鍵字

電路板層級掉落測試 ； 有限單元分析 ； 疲勞壽命預估 ； LS-DYNA分析軟體 ； 銅導線破壞模式

並列摘要

隨著可攜式及手提式電子產品的普及化，高抗摔落性、高可靠度電子產品已成為相關產品研發中的中一項相當重要設計重心。為減低可攜式產品在使用過程中摔落造成的影響，封裝體在掉落衝擊下的動態響應研究儼然成為封裝可靠度研究中十分重要的一環。
本研究針對電路板層級掉落測試實驗、其破壞模式分析、掉落測試動態模擬法、以及封裝體銅導線於掉落測試中之特徵壽命預測模型等方面進行相關研究及分析。其後並針對封裝體提出結構最佳化設計，增強其在掉落測試中的抗衝擊性能。在本研究中利用應力緩衝層增強型封裝體作為掉落測試的測試載具，該應力緩衝層增強型封裝體具有將晶片訊號外擴的功能，並具有優秀的抗掉落衝擊特性，能符合現今對於可攜式電子產品的嚴苛要求。該封裝體具有一相當厚度且具柔軟特性的介電層，該介電層可吸收產品掉落時造成的衝擊，進而保護介電層下的銲錫接點。然而，介電層吸收掉落衝擊時造成的介電層大量變形使內埋在介電層中的銅導線產生變形而破壞。在本研究中，此銅導線破壞模式實為該應力緩衝層增強型封裝體之主要破壞模式，故將針對此破壞模式進行相關研究及分析。
本研究主要發展一銅導線掉落衝擊壽命預測理論，在封裝體產品的設計流程中，壽命預測模型實為一不可缺的重要工具。透過壽命預測模型，研發人員可精確地預估特定封裝體的抗掉落衝擊性能，作為設計新型封裝體之依據。本研究進行掉落測試動態模擬來釐清封裝體遭受掉落衝擊的瞬間造成的物理變形行為。分析結果指出封裝體對於掉落衝擊的動態響應並不像溫度循環測試般具週期性及規則性，其為不規則的動態響應。故傳統金屬疲勞理論較不適用於本研究中所發展之壽命預測模型。封裝體在掉落衝擊下實為一疲勞傷害累積的過程，故本研究引用傷害累積概念作為封裝體疲勞模型的基礎。研究結果發現吾人應以銅導線的累積塑性應變作為壽命預測模型的分析指標。此乃因為掉落測試造成的破壞模式屬於低週期疲勞破壞，而塑性應變為主導低週期破壞最重要的因子。本研究發展之衝擊壽命預測模型與掉落測試實驗具有良好的對比性及關連性，故設計研發人員可根據此壽命預測模型進行相關電腦輔助模擬實驗以加速產品開發的時程。
由掉落測試實驗結果可得知銅導線破壞為該封裝體主要破壞模式，故在結構設計時將以提高銅導線可靠度為主要設計目標。第一部份將先針對銅導線的配置進行相關設計，接著則將封裝體中各層的厚度參數進行參數化分析以求得較佳的設計方向，最後本研究提出以應力緩衝層加強型封裝為基礎改良的三明治結構及縮小晶片尺寸等設計以提高銅導線抵抗掉落衝擊的能力。
基於累積傷害的概念下，本研究提出一銅導線掉落衝擊壽命預測理論。該預測模型可正確的估計封裝體在掉落測試下的可靠度。此外，藉由本研究中提出之封裝體設計流程將有助於降低實驗成本並提高產品研發的時程。

並列關鍵字

board-level drop test ； finite element ； fatigue life prediction ； LS-DYNA ； metal trace failure

參考文獻

79 M. C. Yew, H. P. Wei, C. S. Huang, D. C. Hu, W. K. Yang, and K. N. Chiang, “A study of failure mechanism and reliability assessment for the panel level package (PLP) technology,” Proc. of the 8th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems (EuroSimE2007), pp. 475-482, London, England, April 16-18, 2007.

72 K. N. Chiang, Z. N. Liu, and C. T. Peng, ”Parametric reliability analysis of no-underfill flip chip package,“ IEEE Transactions of Components and Packaging Technologies, Vol. 24, Issue: 4, pp. 635 –640, Dec. 2001

80 M. C. Yew, C. Yuan, C. N. Han, C. S. Huang, W. K. Yang, and K. N. Chiang, “Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-out Capability,” Proc. of the 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA2006), pp. 223-228, Singapore, July 03-07, 2006.

3 JEDEC Solid State Technology Association, JESD22-B111: Board Level Drop Test Method of Component for Handheld Electronics Products, 2003.

5 R. Darveaux, “Effect of simulation methodology on solder joint crack growth correlation,” Proceedings of the 50th Electronic Components and Technology Conference, ECTC, pp. 1048-1058, Las Vegas, USA, May 21-24, 2000.