多重電壓源的低功率及零時序差異之時脈樹設計

Low Power and Zero Skew Clock Tree Design with Multiple Voltages

吳俊德(Ju-De Wu)

指導教授 ： 陳美麗

中原大學/工學院/資訊工程研究所/碩士(2005年)

https://doi.org/10.6840/cycu200500313

摘要

隨著晶片上電晶體的數目快速增加，時脈樹之功率消耗約為晶片功率消耗的 20~50% [4]，因此如何有效的降低時脈樹的功率消耗，將成為不可或缺的考量。此外，現今的晶片設計已走向使用多重電壓源 (Multiple voltages) 的設計方向，故我們希望能以此為前提，來設計一個符合低功率且零時序差異的時脈樹建構演算法。
本篇論文將以設計低功率消耗並符合零時序差異 (zero skew) 的時脈樹為主要目標。在電路擺置過後，將根據所得到的正反器(flip-flops) 位置以及多重電壓源資訊並配合 DME 繞線方式進行時鐘樹合成的動作。在時脈樹的建構方面，會使用加入 clock gates 的方式，節省時脈樹的功率消耗。我們的演算法將使用 bottom-up 的方式而將整棵時脈樹的拓樸 (topology) 建構完成。在 Top-down 階段由之前所得的時脈樹拓樸來將時脈樹繞線完成。最後，在置入階層轉換器 (level converter) 於時脈樹後會再進行調整時脈樹時序差異的部分，使得時脈樹為零時序時脈樹。我們應用實際的電路[19]和 ISCAS’89 的 benchmark [20] 到我們所提出的方法而建構時脈樹，相較於形成多棵單一電壓時脈樹的方法，此二組電路的平均功率消耗分別降低了 22.9% 及 21.94% 。

關鍵字

時脈樹 ； 時序差異 ； 多重電壓源

並列摘要

With the number of transistor in an IC increases quickly, the power consumption of the clock tree accounts for 20~50% [4] of the total power consumption in an IC, therefore, the way to effectively reduce the power consumption of the clock tree is certainly required. Besides, recent IC designs have already been tend to the use the multiple voltages for designs, under this reason, we want to design an algorithm to construct clock tree to conform to the low power and zero-skew requirements.
In this paper, we design a low power and zero-skew clock tree. After cells in the circuit are placed, we apply the location of flip-flops and the information of the multiple voltages to DME routing algorithm to synthesize the clock tree. During the constructing clock tree, we reduce the power consumption of the clock tree by adding clocked gates. In this paper, we use the bottom-up approach to construct the topology of clock tree. In top-down process, we route the clock tree according to the topology of the tree. At the end, after inserting the level converters, we adjust the length of the branches to form a zero-skew clock tree. We apply the circuits in references [19] and the benchmark of ISCAS’89 [20] into our method to construct the clock tree. The experimental results show that comparing to the method of constructing multiple single-voltage clock trees, our method can average reduce the power consumption of these two set of circuits by 22.9% and 21.94% respectively.

並列關鍵字

multiple voltages ； zero-skew ； clock tree

參考文獻

[1] 周堅勇, ”低功率及零時序差異之時鐘樹設計,” 私立中原大學資工研究所碩士論文, 2004.

[15] 劉奕章, ”考慮電壓降之零時序差異時脈樹研究,” 私立中原大學資工研究所碩士論文, 2005.

[6] David Garrett, Mircea Stan and Alvar Dean, “Challenges in Clockgating in a Low Power ASIC Methodology,” in Proc. the International Symposium on Low Power Electronics and Design, 1999, pp. 176-181.

[7] Jaewon Oh and Pedram M., “Gated Clock Routing Minimizing the Switched Capacitance,” in Proc. Design, Automation and Test in Europe, 23-26 Feb. 1998, pp.692-697.

[8] Jaewon Oh and Pedram M., “Power Reduction in Microprocessor Chips by Gated Clock Routing,” in Proc. Asia and South Pacific-Design Automation Conf., 10-13 Feb. 1998, pp. 313-318.