- 學位論文
Grid-Tree: 適用於多核心系統之新型晶片網路
Grid-Tree: A Novel On-Chip Network for Many-cores System
摘要
由於雲端運算與資訊服務的需求日益提升，電腦系統的計算吞吐量亦隨之增加。應用多核心架構開發電腦系統已成為主要的設計方向。然而，當越來越多的處理器核心整合在單一晶片上，用以作為核心間溝通的互聯網路設計顯得更加重要。若互聯網路無法負荷大量核心間的溝通與資料存取，其所造成的效能瓶頸將大幅降低核心增加所帶來的效能增益。有鑑於此，本論文提出一適用多核心架構之新式晶片互聯網路架構︰Grid Tree，並提出Grid Tree互聯網路之連結方式、繞徑方式、交換器設計、與硬體架構規劃。相較於現有互聯網路，如2D Mesh、H-Tree與Fat H-Tree，Grid Tree 具有較高的傳輸效能、較好的晶片可實現性與較低的硬體成本等優點。在本論文中，首先使用理論分析的方式，比較Grid Tree與其他互聯網路的效能與硬體成本的差異。接著採用SystemC模擬實驗，比較Grid Tree與其他互聯網路的實際的傳輸效能。分析與實驗結果顯示︰相較於2D Mesh，Grid Tree的傳輸延遲可減少3倍，且硬體成本可減少2倍。
並列摘要
The continuous growing requirements of cloud computing and information service make the computing throughput of the modern computer systems increase dramatically. The multicore architecture has become the main trend of designing the modern computers. While the integrated processing cores are increased, the interconnection network of the multicore system becomes more important. If the interconnect network cannot afford the huge amount transactions of inter-core communications and data accesses, the increased extra latency will counteract the benefit of adding cores. Accordingly, this thesis provides a novel interconnection network, called Grid Tree, for modern multicore architecture. By cooperating with the provided linking algorithm, routing algorithm, and switching architectures, Grid Tree has higher communication performance, more on-chip fabrication possibility, and lower hardware cost, than conventional on-chip networks, such as 2D Mesh, H-Tree, and Fat H-Tree. In this thesis, the comparisons of performance and area cost among Grid Tree and other interconnection networks are proposed firstly. Than the practical examinations of Grid Tree with other interconnection networks by adopting SystemC simulation are provided. The analysis and experimental results reveal that Grid Tree can provide 3X lower communication latency and 2X lower area cost than 2D Mesh.