用於混合式對映的多通道固態硬碟之混合式通道綁定策略

A hybrid channel binding strategy for multichannel SSDs with hybrid mapping

賴品學(Pin-Shiau Lai)

指導教授 ： 張立平

國立交通大學/資訊學院/資訊科學與工程研究所/碩士(2015年)

https://doi.org/10.6842/NCTU.2015.00359

摘要

近來快閃記憶體因其抗震、便宜、體積小等優勢，被廣泛運用在通訊裝置及儲存裝置中，各家廠商為了追求更高的效能，其內部會採用多通道架構，藉由平行存取各塊快閃記憶體晶片，提升整體的讀寫吞吐量，而多通道的綁定方式一般為了實作上比較容易都是採用靜態綁定的方式，但在一般使用者寫入的情況通道寫入不平均的狀況很明顯，因而導致通道空閒和老化不平均的問題，因此本篇論文題出了一個用於混合式對映演算法上的通道綁定策略，稱為混合式通道綁定，利用空閒的通道幫忙資料較多通道消耗資料，以平衡每個通道的寫入量。實驗結果顯示，我們提出的方法和靜態綁定相比通道空閒度改善了30%左右，通道的入量差異也由原本的30%降低到5%以內。

關鍵字

固態硬碟 ； 綁定

並列摘要

In recently years, because of the higher shock resistance , cheap and small size, flash memory is used widely in communication equipment and storage devices. SSDs enhance the overall performance with adopting a multichannel architecture. Generally, multichannel use static binding because of easy implement. However, the general user write is uneven , and it will result in channel idle and inconsistent aging between channels. This study presents a binding strategy for hybrid mapping FTL, called hybrid channel binding, which use the idle channel to help flush the deepest buffer to balance the amount of written page. Experimental results show that our method compared to static binding improves about 10~30% in idle time, and the amount of the difference channel is reduced form the 30% to less than 5%.

並列關鍵字

SSD ； Channel Binding

參考文獻

[6] Sung Kyu Park, Youngwoo Park, Gyudong Shim, and Kyu Ho Park. 2011. CAVE: channel-aware buffer management scheme for solid state disk. In Proceedings of the 2011 ACM Symposium on Applied Computing (SAC '11). ACM, New York, NY, USA, 346-353.

[10] Hyojun Kim and Seongjun Ahn. 2008. BPLRU: a buffer management scheme for improving random writes in flash storage. In Proceedings of the 6th USENIX Conference on File and Storage Technologies (FAST'08), Mary Baker and Erik Riedel (Eds.). USENIX Association, Berkeley, CA, USA, , Article 16 , 14 pages.

[1] Aayush Gupta, Youngjae Kim, and Bhuvan Urgaonkar. 2009. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. SIGARCH Comput. Archit. News 37, 1 (March 2009), 229-240.

[2] Sang-Won Lee, Dong-Joo Park, Tae-Sun Chung, Dong-Ho Lee, Sangwon Park, and Ha-Joo Song. 2007. A log buffer-based flash translation layer using fully-associative sector translation. ACM Trans. Embed. Comput. Syst. 6, 3, Article 18 (July 2007).

[3] Yang Hu; Hong Jiang; Dan Feng; Lei Tian; Hao Luo; Chao Ren, "Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance," Computers, IEEE Transactions on , vol.62, no.6, pp.1141,1155, June 2013