轉換SystemC TLM模型到RTL模型

Toward Translating SystemC Transaction Level Model to RTL Model

林佳輝(Chia-Hui Lin)

指導教授 ： 鄭福炯

大同大學/電機資訊學院/資訊工程學系所/碩士(2008年)

摘要

電路製程技術的進步使得晶片上的功能愈來愈強大。但這也使得系統設計越來越複
雜。然而電子產品的生命週期卻愈來愈短，更加深了產品上市時程(Time to Market)
的壓力。如何減少系統複雜度以符合上市時程就成為重要的議題。
使用較高層級的TLM 來描述系統比用RTL 更有效率而且快速。在SystemC
TLM 中有許多重要的模組例如處理器和匯流排，其中好的匯流排架構能使得系統運
作得更有效率。本論文研究如何在三種不同的TLM 模型中實作一般匯流排(general
bus)，並且提出了一個方法將SystemC TLM 的一般匯流排轉換成為RTL 的匯流排
模型(WISHBONE 和Avalon)。藉此縮短開發時程以符合上市時程的需求。

關鍵字

轉換 ； 匯流排

並列摘要

The improved circuit design technology makes the functionality on a chip more and more powerful, but this also causes high system design complexity. The life cycle of electronic circuit of products is getting shorter and shorter. This causes more pressure of time to market. How to shorten time to market becomes an important issue.
Describing the system with high-level TLM (Transaction-level model) is more
efficient and faster than describing with RTL (Register transfer level). There are many important modules in TLM such as processor and bus. Well designed bus architecture can make system work efficiently. In this thesis we investigate how to implement general bus in three different TLMs and propose a methodology to translate the TLM general bus to RTL bus model (WISHBONE and Avalon). Our methodology can reduce design complexity and satisfy the requirement in time to market.

並列關鍵字

translate ； SystemC ； TLM ； bus

參考文獻

[1] Open SystemC Initiative, 2006. http://www.systemc.org/

[3] Stuart Swan, Cadence, “A Tutorial Introduction to the SystemC TLM Standard,”

[6] AMBA specification, Rev 2.0, ARM Inc., 1999.

[9] Lukai Cai,Daniel Gajski, “Transaction Level Modeling: An Overview,” First

IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and