p型鍺金氧半場效電晶體與n型鍺金屬接面特性分析

Characterization of Ge pMOSFETs and Contact to N-type Ge

陳鈺升(Yu-Sheng Chen)

指導教授 ： 劉致為

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2014年)

https://doi.org/10.6342/NTU.2014.10021

摘要

隨著摩爾定律的規則，半導體工業持續地將元件微縮化。但傳統的矽金氧半場效電晶體技術已經逐漸達到其微縮的極限。為了要突破物理極限以維持著元件微縮的步調，必須要開發更高載子遷移率的新穎材料來取代傳統矽做為元件通道材料，因此近來鍺或是其它三五族的高載子遷移率材料受到相當的矚目，而其中又以擁有高電洞遷移率以及成熟的矽鍺技術的鍺被視為能在未來使用於22奈米製程節點以下來取代矽。然而，鍺材料仍然存在者許多難題需要克服，例如高介電係數材料的製程整合，參雜物的活化改善，表面鈍化的處理，以及適當的應變技術等等。
霍爾效應的重要性建立在它能準確地提供半導體內的載子濃度、遷移率以及電阻率。以它為基礎的范德堡法更是提供了一個簡單、方便、快速且低成本的實驗來幫助我們萃取出我們想要的參數。它被廣大地運用在半導體業界以及實驗研究室中。我們使用此一方法來量測與檢驗我們的樣品狀況，包括矽、鍺主體晶圓以及鍺的磊晶層薄膜。而這些樣品稍後會應用在其它章節之中來進一步做電晶體的製備與分析。然而，霍爾因子的存在使得霍爾效應量到的參數出現不可忽略的誤差，我們也會一併討論此現象。
本論文中，我們利用了高速熱氧化法來成長二氧化鍺做為鍺與高介電係數材料的介面層，接著使用了氧氣為基底的低溫原子層沉積來生長三氧化二鋁用來保護並增進二氧化鍺的品質，其效應可由鍺金氧半電容元件的電容特性量測得知。此外，我們用多種離子佈值增加參雜的濃度且用了高速熱退火來活化離子佈值，並使用鎳鍺化物來做為電極降低電阻效應而成功製做了高開關比例的二極體。在確立完良好的金屬接面技術以及閘極氧化層堆疊之後，我們實作並分析了p型鍺金氧半場效電晶體的結果。
先前的許多研究大都專注在平面式金氧半場效電晶體，但是近年來，越來越多新穎的想法與概念被應用在電晶體的三維結構上。我們利用磊晶技術將鍺薄膜層生長在絕緣層覆矽晶圓上，再使用反應式離子蝕刻，可以將鍺與矽之間的錯位蝕刻乾淨，進一步形成只有鍺的天橋通道，加上氧化層與閘極堆疊，便形成了環繞式閘極電晶體。我們實作並分析了實驗結果，預測它有著良好的閘極控制能力與比較不嚴重的短通道效應。
對於n型鍺來說，其金屬接面特性一直以來都是待解的問題。越來越多證據顯示出不同金屬的波函數都會被固定在靠近鍺價帶的地方，也因此很難形成完美的歐姆接觸。為了解決此現象，我們實作了不同的金屬接觸，設法找出特性接觸電阻率，進一步討論傳輸線模型的應用與結構修正，並研究蕭基能障高度對於接觸電阻率的重要性。我們預期此問題的解決將可快速地被整合進未來n型鍺電晶體的製程中。

關鍵字

范德堡法 ； 霍爾因子 ； 鍺 ； 金氧半場效電晶體 ； 無接面 ； 閘極環繞式電晶體 ； 傳輸線模型 ； 特性接觸電阻率 ； 蕭基能障高度

並列摘要

Recently, semiconductor industry has followed the path of scaling trend based on Moore’s law. But conventional bulk Si MOSFETs is approaching its fundamental scaling limits. To continually scale the device, high mobility materials have been comprehensively investigated as channel material for replacing Si, such as Ge or III-V material due to its high intrinsic carrier mobility. Ge has become a promising candidate for 22nm nodes beyond CMOS technology due to its compatibility of Si-based technology. However, there are several critical issues for Ge devices. The primary challenges to achieve high mobility Ge MOSFETs are the high-k integration process, the improvement of dopants activation, reduction of interface traps density, and proper strain configuration.
The importance of the Hall Effect is supported by the need to determine accurately carrier density, electrical resistivity, and the mobility of carriers in semiconductors. The Hall Effect and the following development of Van der Pauw method provides a relatively simple and convenient method owing to its simplicity, low cost, and fast turnaround time, it is an indispensable characterization technique in the semiconductor industry and in research laboratories. Nevertheless, the concept of Hall factor will influence the accuracy of the parameter by experiment. We will discuss the phenomena latter.
In this thesis, rapid thermal oxidation (RTO) is used as the fast and effective Ge interface passivation. Al2O3 as high-k layer is deposited by atomic-layer-deposition (ALD) using molecular oxygen (O2) as oxidant at low temperature. The electrical characterizations by dispersion-free C-V curves of Ge MISCAPs are investigated. Moreover, high on/off ratio p+/n diodes were fabricated by two steps ion-implantation and rapid thermal annealing for activation. In addition, The NiGe contact is used to improve the contact resistance. After all, the good performance of p-MOSFET with NiGe contact will be demonstrated.
Recently researches have shown more and more 3D novel structures to fabricate better performance of MOSFETs. Our goal is to utilize epitaxial Ge on SOI, trying to fabricate Gate-All-Around (GAA) p-MOSFETs. Using RIE to etching the dislocations near Ge/Si interface. We can construct a bridge-channel which can be encircled by gate stack, thus achieving GAA structure to enhance gate control and reduce short channel effect. The characteristic of GAA pFETs is also be demonstrated.
Contacts to n-type Ge are always a problem to the semiconductor industry. More and more evidences show that strong Fermi-level pinning near the germanium valence band due to metal-induced gap states at metal/germanium interface. Our purpose is to test the probability of n-type Ge contacts and to find out the best solution as now. We will try to calculate the TLM model and the specific contact resistivity. Finally the Schottky barrier height is discussed here.

並列關鍵字

Van der Pauw method ； Hall factor ； Germanium ； MOSFET ； Junctionless ； GAA ； Transmission Line Model ； Specific Contact Resistivity ； Schottky Barrier Height

參考文獻

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