具有電源電壓雜訊抑制功能之全數位延遲鎖定迴路

All-Digital Delay-Locked Loop with Supply Noise Suppression Technique

蔡家豪(Chia-Hao Tsai)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.10023

摘要

現今的記憶體系統因為製程技術的進步而造就了大容量之產品問世，這也代表記憶體系統的集約程度也因此而越來越高，使得電路模組之間的資料傳遞與運作時序的安排也相對的跟著複雜了起來，如何讓電路模組之間的工作時脈同步顯然成為了一個重要的議題；而記憶體系統為了達到省電的效果，發展出一種會根據工作量來切換重載和輕載的工作模式，以降低記憶體系統的功率消耗，但此操作模式會造成電源供應的電壓產生雜訊，進而影響到電路模組的工作效能。有鑑於此，記憶體系統所面臨的時脈同步與電壓雜訊之問題越顯嚴重。
本論文除了介紹延遲鎖定迴路與電源電壓校正技術的基本概念之外，並且提出兩種具有電源電壓校正功能之全數位延遲鎖定迴路，以解決上述記憶體系統之中所碰到的問題。其中一種以直流電壓準位為校正基礎的全數位延遲鎖定迴路利用電源電壓偵測器來偵測出目前的系統額定電壓，並且依據偵測的結果補償一組電源電壓偵測碼進入數位控制延遲線之中，以克服全數位延遲鎖定迴路無法快速追回因系統額定電壓變換所造成的殘餘相位誤差，進而使回復鎖定時間也得到改善；在450MHz，系統額定電壓下降0.08V時，有校正機制與無校正機制的回復鎖定時間分別為43ns與130.00ns。最後利用0.13-μm one-poly eight-metal CMOS製程來實現出面積為1.27 x 1.27 mm2的晶片，其功率消耗為13.2毫瓦，操作頻率範圍由450MHz到650MHz。
本論文中另外一種以相位誤差為電源校正基礎的全數位延遲鎖定迴路是利用電源電壓校正器來偵測輸出時脈與輸入時脈的殘餘相位誤差，藉此來判斷是否有系統額定電壓準位飄移的狀況發生；如果電源電壓校正器判斷出此時發生系統額定電壓準位飄移的狀況，則會依據偵測的結果補償一組校正碼進入數位控制延遲線之中，以克服全數位延遲鎖定迴路無法快速追回因系統額定電壓變換所造成的殘餘相位誤差，進而使校正之後所需要的回復鎖定時間壓制在80個輸入時脈週期之內，並且利用0.18-μm one-poly six-metal CMOS製程來實現出面積為1.1 x 1.1 mm2的晶片，其功率消耗為10.8毫瓦，操作頻率範圍由250MHz到600MHz。

關鍵字

全數位延遲鎖定迴路

並列摘要

The products of memory system with big volume are cause of the advances in CMOS technologies, which means the intensive degree of memory system is higher, too. When the number of module in the integrated circuit and system becomes larger, the data communication and timing arrangement between modules are more complex, that’s why the topic of synchronization becomes more and more important. And that the memory system will change the operating mode between heavy load and light load alternately to save the power consumption of the whole system. Apparently, the problems of synchronization and noise in power supply voltage are more serious in the memory system.
In this thesis, besides introducing the basic concept of delay-locked loop and power supply calibration technique, two kinds of all-digital delay-locked loop with supply voltage calibration technique are proposed to overcome the problems mentioned above. One kind of all-digital delay-locked loop with supply voltage calibration technique is using supply detector to detect the value of power supply voltage, based on the result of detection to generate supply detection codes, and that put the codes into the digitally controlled delay line to calibrate the residual phase error caused by the drift of supply voltage, the relock time will also be improved. When the value of power supply voltage is from 1.2V to 1.12V, the relock time with calibration and without calibration is 43ns and 130ns. This is fabricated in 0.13-μm one-poly eight-metal CMOS process, the whole chip area is 1.27 x 1.27 mm2, the power consumption is 13.2mW, the operation range is from 450MHz to 650MHz.
In this thesis, another kind of all-digital delay-locked loop with supply voltage calibration technique is using power supply calibration circuit to detect the residual phase error between clkin and clkout to know if the value of power supply voltage changes. If the power supply voltage changes, calibration codes will put into the digitally controlled delay line to calibrate the residual phase error caused by the drift of supply voltage, the relock time will also be limited under 80 reference clock periods. This is fabricated in 0.18-μm one-poly six-metal CMOS process, the whole chip area is 1.1 x 1.1 mm2, the power consumption is 10.8mW, the operation range is from 250MHz to 600MHz.

並列關鍵字

ADDLL

參考文獻

[1]B. Razavi, “Monolithic phase-locked loops and clock recovery circuits : theory and design,” IEEE press, 1996

[3]M. G. Johnson and E. L. Hudson, “A Variable Delay line PLL for CPU- Coprocessor Synchronization” IEEE Journal of Solid-State Circuits, vol. 23, no. 5, pp 1218-1223, Oct. 1988.

[4]A. Efendovich, Y. Afek, C. Sella, and Z. Bikowsky, “Multifrequency Zero-Jitter Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 29, no. 1, pp 67-70, Jan. 1994.

[6]B. J. Chen “All-Digital Fast-Locking Delay-Locked Loop with Duty Cycle Correction,” Master thesis, June 2006.

[9]G. K. Dehng, J. M. Hsu, C. Y. Yang, and S. I. Liu, “Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp 1128-1136, Aug. 2000.