資料群集處理技術在半導體良率預測上之應用

Implementation of GMDH into the Yield Model in Semiconductor Process

梁瑞明(Jui-Ming Liang)

指導教授 ： 陳雲岫

元智大學/工程學院/工業工程與管理學系/碩士(2001年)

摘要

半導體良率在整個半導體製造過程中佔有相當重要的地位。良率的高低代表著製程能力的好壞，能夠瞭解良率並預測良率，便能控制與管理良率；對於企業而言，有高的良率就代表著製程相當穩定，可以為企業減少不良品的損失，進而提高企業的利潤。傳統良率的預測常使用卜瓦松模式(Poisson Model)或負二項模式(Negative Binomial Model)等良率模式來進行預測與分析。但傳統良率模式中對於良率的預測有許多的限制，而且半導體製造技術的進步，也使得過去所使用之良率模式產生較大之誤差與不適用性。
有鑑於此，在本研究中將提出以資料群集處理技術(Group Method of Data Handling；GMDH)來尋求較佳的預測模式來預測良率，利用資料與系統本身自我衍生的方法決定預測模式型態並進行預測。如此，可解決製程複雜性對建構良率模式的影響，並提出一個通用性與良好預測良率的方法。本文中並以模擬來驗證本研究中所提出之良率模式的效果，確實比傳統良率模式有較佳的預測效果。

關鍵字

積體電路 ； 良率模式 ； 資料群集處理技術

並列摘要

In the process of integrated circuit (IC) manufacturing, the yield play an important role. A high yield can bring profit to the industry, thus how to achieve high and stable yield is a principal task for the business. Good yield models can help us forecasting the yield precisely. However, the conventional yield models, such as poisson or negative binomial yield models can not meet the needs of the modern technology of the semiconductor manufacturing. Therefore, in thesis, we propose a new yield model which is established by the algorithm of Group Method of Data Handling (GMDH). We can establish the yield model by the data only without any assumptions of the yield model. The proposed approach get a better forecasting results than the conventional yield models. Simulation study is performed to show that the GMDH model is more reliable than the conventional yield models are.

並列關鍵字

integrated circuit ； yield model ； Group Method of Data Handling

參考文獻

5. A. G. Ivakhnenko, V. V. Shervashidze et, “Discovery of Physical Laws by GMDH Method with the Absence of Bais Criterion,” Sov. Autom. Control, 6, 32-45 , 1972.

8. Cunningham, James A., “The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing” IEEE Trans, Vol.3, No.2, 60-71, 1990.

10. Gurber, H., Learning and Strategic Product Innovation: Theory and Evidence for Semiconductor Industry, Amsterdam, The Netherlands, 1994.

11. Murphy, B. T., ”Cost-size Optimum of Monolithic Integrated Circuits,” Proc. IEEE, Vol. 52, pp.1537-1545, 1964.

12. Mullenix, P., Zalnoski, J. and Kasten, A.J., “Limited yield estimation for visual defect source,” IEEE Trans. Semiconduct. Manufact., 10, 17-23 , 1997.