懸浮閘電晶體於0.18μm單層多晶矽CMOS製程之開發與其在類比電路上的應用

Floating Gate MOSFET in 0.18μm Single-Poly CMOS Process and Its Applications on Analog Circuits

王博平(Po-Ping Wang)

指導教授 ： 鄭桂忠

國立清華大學/電機資訊學院/電機工程學系/碩士(2010年)

摘要

在積體電路發展的歷程中，懸浮閘元件經常被用來製作非揮發性( Nonvolatile )記憶體，如EPROM、快閃記憶體等。由於懸浮閘元件可相容於標準CMOS製程中，九○年代開始，有許多研究則將其做為設計類比電路時的一種方法。近年來，隨著製程技術的日益精進，懸浮閘元件的製作方式也必須有所改變，本論文提出一個可於0.18μm單層多晶矽CMOS製程中製作的懸浮閘元件，並且能夠將其應用於類比電路設計上。
本論文提出的懸浮閘元件結構，係由三個PMOS所組成，元件的寫入操作採用離子化熱電子注入與帶對帶穿隧電流，抹除操作則為FN 穿隧效應，同時亦嘗試以通道熱電洞注入機制做為抹除操作。本論文驗證元件在寫入與抹除操作時的電性變化，元件耐久度與資料保久度的實驗數據也會在論文中提出。
為了能夠以SPICE模擬懸浮閘元件在電路操作時的特性，本論文透過熱電子注入電流與FN穿隧電流模型的建立，提出此元件的等效電路模型；並將實驗測量結果與模擬結果相互比較，驗證此模型的近似效果。本論文進一步將懸浮閘元件用於類比記憶體電路的設計，期望能透過電路的操作，適性地控制懸浮閘電壓，並將此元件推展至其他電路的應用。
最後，針對Translinear電路在標準CMOS製程中製作的諸多限制，本論文應用懸浮閘元件提出一個新的Translinear 電路設計方案，藉由改變電晶體的電壓電流轉換關係，期望能夠減小Translinear電路在操作時的誤差；並以電流公式的推導與電路模擬結果，驗證此方案的可行性。

關鍵字

懸浮閘 ； 0.18 um CMOS 製程 ； 單層多晶矽 ； Translinear ； FGMOS

並列摘要

During the years of integrated circuits (IC) development, floating gate device has been used to implement nonvolatile memories, such as EPROM, flash memory, etc. Due to its very good compatibility with standard CMOS process, since the 90's, floating gate device has been treated in some studies as an analog circuit element in the analog circuit design. As the technology moves into submicron and even deep-submicron processes, more attention needs to be paid to utilize floating gate device as an analog element. This study proposes a floating gate device that can be used in analog circuit design. This floating gate device has been fabricated in a single poly 0.18μm CMOS process,
The proposed floating gate device is constructed with three P-channel MOSFETs. The device is programmed by ion impact hot electron, and erased by FN tunneling. In addition, erasing operation by channel hot hole injection mechanism is also studied. Experimental data of electrical characteristics during programming and erasing, device endurance, and data retention is given in this study.
In order to simulate the characteristics of the floating device by SPICE in circuit design, this study build up a SPICE compatible effective circuit model of the floating gate device, by building up the hot electron injection current model and the FN tunneling current model. Experimental data is compared with simulation results to verify the accuracy of this effective circuit model. This model provides a simulation tool for using the floating gate device as an circuit element in the circuit design.
This study concludes with a novel application of the floating gate device in analog circuit. To deal with many restrictions of traditional translinear circuits in standard CMOS process, this study proposes to utilize floating device as a solution. By modifying the current-voltage relationship of the transistor, reduction of errors from the translinear circuit are expected. Formula deduction and circuit simulation are both used to verify the feasibility.

並列關鍵字

Floating gate ； 0.18 um CMOS Process ； Single poly ； Translinear ； FGMOS

參考文獻

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