可操作於超低電壓並具有回寫感測放大器之靜態隨機存取記憶體電路設計

Ultra Low Voltage SRAM with Write Back Sense Amplifier Circuit Design

鄒柏瑋(Po-Wei Tsou)

指導教授 ： 張孟凡

國立清華大學/電機資訊學院/電機工程學系/碩士(2010年)

摘要

在我們的生活環境中，可在諸多的電子產品中發現靜態隨機存取記憶體的蹤影;然而，同樣在系統單晶片之中，相對於其他的電路需要占據較多的面積。 這個現象表示靜態隨機存取記憶體在單晶片中有較大的功率消耗。所以，要如何解決靜態隨機存取記憶體功率消耗的問題而又不會降低其操作性能，這是一個極大挑戰。
對於降低靜態隨機存取記憶體功率消耗最關鍵的點，就是降低其操作電壓。但是，降低操作電壓將會造成靜態隨機存取記憶體之記憶單元的穩定性會有所下降。而當靜態隨機存取記憶體操作在超低電壓時，不論是在在寫入模式或是讀取模式，這種現象將會造成非選取的記憶單元所儲存的資料發生錯誤。因此，若因為這種現象而造成靜態隨機存取記憶體寫入或是讀取失敗，對於操作在超低電壓之目的就沒有任何意義。
在本篇論文中， 提出一個回寫感測放大器來解決靜態隨機存取記憶體之記憶單元如上所述的問題；而這個回寫感測放大器還能幫助靜態隨機存取記憶體操作於超低電壓。並且，透過對於放大器佈局的方式，像是一維或是二維的共點及一間格或兩接格的佈局來降低放大器之補償電壓，使得放大器即使操作在超低電壓也能透過極小字元線之電壓差成功感測資料。
為了能測試和證明，透過九十奈米互補式金氧半製程技術，建構出一個容量為六十四千字元(64kb)的靜態隨機存取記憶體積體電路並搭配上所提出之二維共點佈局方式的回寫感測放大器。藉由示波器及國家晶片中心之單晶片系統測試機台來測試晶片，量測結果顯示這顆六十四千字元(64kb)的靜態隨機存取記憶體積體電路可操作在供應電壓為兩百三十毫伏之下，同時操作頻率可達一點三百萬赫茲。因受惠於操作在兩百三十毫伏之下，此靜態隨機存取記憶體積體電路之功耗為十五點三六微瓦，能量消耗為三十二點四七微微焦耳。

關鍵字

超低電壓 ； 靜態隨機存取記憶體

並列摘要

In our livelihood, the Static Random Access Memory (SRAM) appears in the almost electronics and it is required more area than other circuits in the SOC chip. That shows the SRAM used up the most power of a chip. So, how to solve the problem of SRAM power consumption and not to cut down the SRAM operating performance is a big challenge.
The point about all problems of SRAM for reducing the power consumption is to lower the SRAM operating voltage. But, pulling down the operating voltage that made the static noise margin (SNM) of SRAM cell characteristics be smaller. This phenomenon will to cause the read half-selected disturb problem and write half-selected disturb problem when SRAM macro operating in write mode or read mode in the ultra low voltage. If SRAM macro happens the disturb problem which made the write fail or read fail, that is no meaning for to operate at ultra low voltage.
In this work, we proposed a differential read write back sense amplifier (DRWB-SA) to cancel the write half-selected disturb problem of SRAM cell. This DRWB-SA will help the SRAM to operate at the ultra low voltage. And, we analysis the SA layout style about 1 dimension or 2 dimension common-centroid and one-pitch or two-pitch to reduce the SA offset, which is made DRWB-SA can success operating at ultra low voltage by small bit line (BL) swing.
To test and verify, we proposed a 64kb SRAM macro with DRWB-SA that is used two-pitch common-centroid layout is fabricated in 90nm CMOS technology. By oscilloscope and CIC 93K tester to get measurement results of the 64kb SRAM macro, that can operate down to 230mV running at 1.3MHz. Benefiting from operation at 230mV, the operating power of SRAM is 15.36uW and 32.47pJ in energy consumption.

並列關鍵字

Ultra Low Voltage ； SRAM

參考文獻

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