高介電閘極氧化層和金屬閘極於矽和三五半導體之研究

The study of high k dielectrics and metal gates on Si and III-V semiconductor substrates for the advanced CMOS technology

吳彥達(Yan-Dar Wu)

指導教授 ： 黃倉秀 ； 洪銘輝 ； 郭瑞年

國立清華大學/工學院/材料科學工程學系/博士(2012年)

摘要

展望未來半導體產業發展，元件尺寸持續縮小至15nm以下，高介電常數的閘極氧化物其介電係數需高於30以上，並且需高載子遷移率的通道材料取代使用SiO2/Si系統。另外，高介電常常數介電材料及三五化合物半導體也必須要能夠被整合在Si上。
本論文的研究主題分為三個部分:
一、在矽基板上，利用MBE成長的高介電氧化鉿薄膜作為基板，可以減少濺鍍成長氧化鉿時介面層的生成。高解析度穿遂式顯微鏡（High resolution transmission electron microscopy, HR-TEM）證實使用高介電氧化鉿薄膜作為基板介面層厚度(9 Å)，較直接在矽基板成長介面層厚度(19Å)減少一半的厚度。以高介電氧化鉿作為基板與直接成長在矽基板的電性結果分別顯示介電值（dielectric constant, κ）為12.8和11.4、電容等效厚度(capacitance equivalent thickness, CET) 為1.8nm和2nm、漏電流密度為8.1x10-7A/cm2 and 3.8x10-3A/cm2。良好的電性結果顯示串連在氧化物和半導體的低介電層大幅減少。
二、利用濺鍍方式在氧化鉿(HfO2)摻雜鈦(Ti)，由於氧化鈦擁有高介電係數約50-80，在氧化鉿裡加入鈦，可大大提升薄膜的介電係數。分別以矽晶圓和MBE成長的高介電氧化鉿薄膜為基版，將HfO2摻雜鈦Ti成長在其上，來進行研究。高解析度穿遂式顯微鏡（HR-TEM）證實使用高介電氧化鉿薄膜作為基板介面層厚度(8Å)，直接在矽基板成長介面層厚度(12 Å)。以高介電氧化鉿作為基板與直接成長在矽基板的電性結果分別顯示介電值（κ）為21.4和13.4、電容等效厚度(CET) 為1.6nm和2.2nm、漏電流密度為2x10-2 A/cm2 and 0.31A/cm2。
三、氧化鋁(Al2O3)/氧化鎵與氧化釓(Ga2O3(Gd2O3))/砷化鎵銦組合(In0.2Ga0.8As)經850oC高溫退火後，成長鋁和鎳當電極。由高解析度穿遂式顯微鏡分析得知氧化物層經高溫退火後仍維持非結晶性(amorphous)，氧化物和半導體介面非常清晰。電性方面，在電容電壓(capacitance-voltage)特性上，表現出很小的頻散(frequency dispersion)，顯示費米能階在整個能帶隨著閘極電壓而自由調變；在同一金屬電極的條件下，平帶電壓(flat band voltage)不隨頻率改變，若換成另一種金屬電極，平帶電壓仍不隨頻率改變，顯示出平帶電壓只有隨著金屬的功函數(work function)在改變， 代表在金屬和氧化物介面上費米能階是自由的不會被釘拴(Fermi level unpining)。此外，我們推導不同電極在p-型和n-型電容上臨界電壓(threshold voltage)，與準靜態電容電壓(quasi-static CV)觀察之結果相當吻合。

關鍵字

氧化鉿 ； 氧化鈦 ； 金屬閘極 ； 高介電係數氧化物 ； 矽基板 ； 三五半導體

並列摘要

Looking beyond the 15 nm node ICs, the consensus is that not only high-κ dielectrics but also appropriate channel material should replace the long-standing SiO2/Si system. The combination of high-κ dielectrics with channel of the III-Vs will have to be integrated onto Si.
The themes of this work were divided into three parts:
1. Silicon wafer and MBE-grown HfO2 thin template were used as substrates for sputtering deposition. From TEM pictures, the interfacial layer thickness of HfO2 deposited on Si and MBE-grown thin HfO2 template is 19.3 Å and 9 Å. At -1V, the leakage density is 3.8x10-3A/cm2 and 8.1x10-7A/cm2 for HfO2/Si and HfO2/(MBE-grown thin HfO2 template) samples. For HfO2/(MBE-grown thin HfO2 template) sample, a maximum value of capacitance at 1 kHz is 151pF, yielding a dielectric constant of 12.8 with the capacitance equivalent thickness (CET) of 17.8Å. The capacitance-voltage curves of HfO2/(MBE-grown thin HfO2 template) sample show a minor frequency dispersion of capacitance. The interfacial improvement and the enhanced electrical properties of the HfO2 film were obtained with MBE-grown thin HfO2 template.
2. HfO2 was combined with TiO2 to increase the dielectric constant. From TEM, the oxide thickness of Ti-doped HfO2 on Si and MBE-grown HfO2 template is 76 Å and 87 Å. The thickness of interfacial layer for Ti-doped HfO2 on Si and MBE-grown HfO2 template is 12Å and 8Å. At Vfb+1V, the leakage current density of Ti-doped HfO2 on Si and MBE-grown HfO2 template was 0.31 and 2x10-2 A/cm2. According to the CV curves, the calculated flat-band voltage of the Ti-doped HfO2 on Si and MBE-grown template was 0.15 and 0.28 volt. From the CV curves modified with two-frequency model, the calculated dielectric constant of Ti-doped HfO2 on Si and MBE-grown template is 13.4 and 21.4 with capacitance equivalent thickness of 22Å and 16 Å.
3. For the Al2O3/Ga2O3(Gd2O3)/In0.2Ga0.8As system, an atomically sharp oxide/semiconductor interface and amorphous GGO without any re-crystallization indicates the robustness and thermal stability of the hetero-structures. Both p- and n-MOS capacitors show very small frequency dispersion ranging from 2.2% to 4.4% (10 kHz–500 kHz) in the accumulation region, indicating the high-quality gate dielectric stack and GGO/In0.2Ga0.8As interface. For MOS capacitors with the same type of substrate and different metal gates, the differences between the Vfb’s are in good agreement with the differences in metal work functions, indicating unpinned Fermi-levels at the metal/dielectric interfaces. These are due to the perfected interfaces on both oxide/semiconductor and metal/oxide, revealing Fermi- level unpinning at both interfaces. Moreover, we have further derived the Vth’s of the p- and n-MOS capacitors with different metal gates. The present derived Vth values may not be very accurate, however, are in a good agreement with those observed on quasi-static C-V curves.
In summary, the results in this dissertation demonstrate MBE-grown thin template is a good buffer layer to decrease the plasma bombardment during the sputtering process, mixing TiO2 into HfO2 is effectively to increase the dielectric constant value, and Vth’s of the p- and n-MOS capacitors with different metal gates was derived.

並列關鍵字

HfO2 ； TiO2 ； Metal gate ； high-k dielectric ； Si wafer ； III-V semiconductor

參考文獻

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Chapter 1

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