Title

應用於電阻式隨機存取記憶體之製程變異容忍感測電路

Translated Titles

A Process Variation Tolerant Sensing Circuit for RRAM

Authors

林谷峰

Key Words

電阻式記憶體 ; 感測放大器 ; 製程變異容忍 ; RRAM ; Sense Amplifier ; Process Variation Tolerant

PublicationName

清華大學電機工程學系所學位論文

Volume or Term/Year and Month of Publication

2010年

Academic Degree Category

碩士

Advisor

張孟凡

Content Language

英文

Chinese Abstract

近年來,可攜式裝置對於讀取操作速度要求越來越高,一些新興的非揮發性記憶體有著克服快閃記憶體之寫入效能和製程微縮限制的潛力,其中,電阻式隨機存取記憶體的寫入時間能夠少於十奈秒,如此一來,讀取時間將成為高效能應用的瓶頸。此外,電阻式記憶體細胞的讀取電壓必須低於零點三伏特以避免干擾的現象發生,但傳統電流感測讀取電路的位元線箝制電壓容易受到製程和溫度的影響。另外,參考細胞阻值變異會造成參考電流漂移而導致讀取失敗。 本論文中,我們提出一個製程變異容忍感測讀取電路,具有偵測並補償製程和溫度變異能力避免讀取干擾、窄分布參考電流產生機制減少讀取失敗的發生機率以及位元線充電速度提升機制縮短位元線讀取時的充電時間。藉由以上我們提出的方法和機制來達到高速、可靠的讀取操作。 我們製作了一個四百萬位元非同步電阻式記憶體之完整功能電路,使用零點一八微米互補金氧半技術以及工研院的電阻元件技術,讀取電路操作電壓為一點八伏特。我們量測兩千零四十八個記憶細胞和五百一十二組參考電流產生器,相較之下,提出之參考電流產生器變異量減少百分之四十五。在四百萬位元電路中量測到的讀取時間在隨機讀取操作與連續讀取操作下分別為七點二奈秒與三點六奈秒。

English Abstract

In recent years, higher and higher read/write speed is also required for high-performance portable equipment. Emerging NVMs have the potential to overcome the write performance and scalability limits of currently dominant Flash memories. The write time of RRAM can be less than 10ns, the read time will be bottleneck for high-speed applications. Besides, the read BL bias of RRAM cells has to be lower than 0.3V to prevent disturb, however, BL voltage of conventional current sensing circuit is sensitive to process and temperature variations. In addition, the reference cell resistance variation will cause read failure due to reference current variation. In this work, we propose a process variation tolerant read circuits featuring detection and compensation of process and temperature variations to avoid read disturbance, narrow-distribution reference generation scheme reduces the probability of read failure, and BL charging speed enhancement scheme shortens BL charging time. The proposed schemes enable high-speed and reliable read operation. An asynchronous 4M-bit RRAM testchip were fabricated in 0.18μm, 5-metal CMOS technology and ITRI resistive device technology with a nominal supply voltage of 1.8V for read circuits. We measured the current distribution of 2048 cells and 512 reference generators, the reduction of reference current variation is about 45% compared to normal LRS cell current distribution. The measured read time of random access and burst access are 7.2ns and 3.6ns respectively.

Topic Category 電機資訊學院 > 電機工程學系所
工程學 > 電機工程
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