Title

數位電路傳輸品質之統計評量

Translated Titles

Statistical Evaluation of Transmission Quality for Digital Logic Circuits

Authors

龔彥中

Key Words

數位電路 ; 傳輸品質 ; transmission quality ; digital logic circuits

PublicationName

中央大學電機工程學系學位論文

Volume or Term/Year and Month of Publication

2007年

Academic Degree Category

碩士

Advisor

陳竹一

Content Language

繁體中文

Chinese Abstract

隨著數位電路工作頻率的提升,信號受到時序抖動以及時脈偏移的影響也越來越劇烈。本篇論文將以正反器串做為模型,並且利用統計分析的方法,來分析數位電路傳輸時受到時序抖動以及時脈偏移影響時的傳輸品質。應用分析的結果找到最佳的時序設定,供設計者參考以提昇電路工作的可靠性。

English Abstract

As the frequency of digital logic circuit rises up, the influence of jitter and skew on the signal is getting more serious. In this thesis we build a model based on a D flip-flop chain and use a statistical method to evaluate the transmission quality of digital logic circuit affected by jitter and skew. The best timing setting can be determined and provided to designers to improve the circuit reliability via this evaluation.

Topic Category 資訊電機學院 > 電機工程學系
工程學 > 電機工程
Reference
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    連結:
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    連結:
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    連結:
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Times Cited
  1. 吳育星(2010)。在矽前完整傳輸評估流程中利用擺幅控制法達成訊號品質最佳化。中央大學電機工程研究所碩士在職專班學位論文。2010。1-69。
  2. 林瑋玲(2016)。可操作於 1GHz至3GHz之全數位、抗變異、低功耗、高解析度時脈抖動量測電路。中正大學電機工程學系學位論文。2016。1-111。