低功率晶片在後擺置階段之電壓源區域建構及多重電壓源元件置換

黃鉦凱

doi:10.6840/cycu200500314

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低功率晶片在後擺置階段之電壓源區域建構及多重電壓源元件置換

Voltage Area Construction and Voltage Scaling at Post Placement Stage for Low Power IC Design

黃鉦凱 , Masters　　Advisor：陳美麗　　

繁體中文 DOI： 10.6840/cycu200500314

電壓源區域；多重電壓源元件置換；低功率設計；後擺置階段； low power design ； voltage scaling ； post placement stage ； voltage area

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With the improvement in process technology, the number of cell on the ICs increases dramatically. Therefore it is essential to study the mechanism in saving the power consumption of an IC. In this paper, we propose a voltage scaling technique with multiple supply voltages to reduce the power consumption on a chip.
	In contrast to the current multiple supply voltages design flow, we perform the voltage area construction and voltage scaling at post placement stage in stead of the synthesis stage. It is because after placement the timing may be estimated more accurately.
	There are two major phases in our algorithm. In the first phase, the slack value of standard cells is utilized to construct a Critical Region Search Tree of smaller slack cells, and then the high voltage region is formed. In the second phase, according to the voltage region of standard cells, we perform voltage scaling and insert level converters. After this phase, if timing violation occurs, we apply gate sizing technique to fix timing violation.
	Experimental results show that this proposed technique can reduce about 20% power consumption of a chip without any timing violation.

Reference ( 10 ) 〈TOP〉

[1] USAMI, K., and HOROWITZ, M. ,”Clustered voltage scaling technique for low-power design”, ISLPED’95 , 1995.
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[2] Jou, J.-Y., Chou, D.-S.,” Sensitisable-path-oriented clustered voltage scaling technique for low power”, Computers and Digital Techniques, 1998 , Page(s):301 – 307.
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[3] Murugavel, A.K., and Ranganathan, N.,”Gate sizing and buffer insertion using economic models for power optimization”, Proceedings of 17th International Conference on VLSI Design,2004, Page(s):195 – 200.
連結：
[5] Dongku Kang, Mark C. Johnson, and Kaushik Roy, ” Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.” , ICCD , 2003, 412-418.
連結：
[6] Chang, M.H., Ting, J.K., Shy, J.S., Chen, L., Liu, C.W., Wu, J.Y., Pan, K.H., Hou, C.S., Tu, C.C., Chen, Y.H., Sue, S.L., Jang, S.M., Yang, S.C., Tsai, C.S., Chen, C.H., Tao, H.J., Tsai, C.C., Hsieh, H.C., Wang, Y.Y., Chang, R.Y., Cheng, K.B., Chu, T.Y., Yen, T.N., Wang, P.S., Weng, J.W., Hsu, J.H., Ho, Y.S., Ho, C.H., Huang, Y.C., Shiue, R.Y., Liew, B.K., Yu, C.H., Sun, S.C., and Sun, J.Y.C.,” A highly manufacturable 0.25 μm multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology” Symposium on VLSI Technology Digest of Technical Papers,9-11 June 1998, Page(s):150 – 151
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