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  • 學位論文

應用於5G及衛星通訊系統之發射機關鍵元件設計與研究

Design and Research of Key Components of Transmitter for 5G and Satellite Communication System

指導教授 : 黃天偉
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摘要


隨著第五代行動通訊(5G)及衛星通訊的發展,毫米波的研究與應用逐漸成現今的趨勢。然而,對於頻寬及更高的傳輸速率需求與日俱增,現今無線通訊頻率主要在6GHz以下已經相當飽和,因此往更高頻率設計為重要的技術發展。其中,28 GHz及38 GHz為第五代行動通訊主要潛在發展頻段,而19 GHz及29 GHz為衛星通訊主要使用頻段。在無線通訊系統中,收發機的設計相當重要及關鍵,本篇論文著重於發射機關鍵元件的設計與研究。 本篇論文主要分成三個部分: 第一部分(第二章)為一個設計在29 GHz的高鏡像抑制升頻混頻器,應用於衛星通訊系統的發射機上。其中為了在發射端27~31 GHz頻段達到比較好的鏡像抑制及隔離LO端訊號的干擾,在混頻器架構上選擇IQ及雙平衡架構。因此在中頻及本地振盪頻率輸入端使用四相位輸入,而發射端使用Wilkinson功率結合器將IQ訊號合成產生鏡像抑制效果。在中頻部分使用多相位濾波器產生四相位,本地振盪頻率則使用90度及180度耦合器產生四相位。此外,因相位產生器損耗較大,故在中頻輸入端加入inverter放大器提升整體電路增益以利系統的應用。 第二部分(第三章)為一個設計在29 GHz的可調式相位轉換器。使用台積電CMOS的180nm製作。此可調式的相位轉換器是將開關式相移器(STPS)和反射式相移器(RTPS)架構作結合。開關式相移器提供180度的相位轉換,而反射式相移器使用控制偏壓產生180度相位調整的功能,兩者結合去設計一個360度相位可調式的相位轉換器。此結合的架構可將開關式相移器及反射式相移器的優點加成,缺點互補為主要設計概念。 第三部分(第四章)為一個設計在38 GHz的高效能功率放大器。使用台積電CMOS的28nm製作,首先分析28nm製程在不同電晶體大小及架構下的特性,並找出能產生最好的效能的電晶體大小及架構去設計功率放大器。並且使用變壓器的功率結合器提高輸出功率同時擁有電路匹配及提供偏壓路徑的功能,此變壓器功率結合器可減少整體電路損耗進而提供整體電路效率。此外在電路架構上加上中和電容可降低電晶體寄生電容使整體電路更加穩定。

並列摘要


With the development of the fifth generation mobile communication (5G) and satellite communication, the research and application of millimeter wave has gradually become the trend of today. However, the demand for bandwidth and higher transmission rates is increasing day by day. Today's wireless communication frequencies are quite saturated below 6 GHz, so designing to higher frequencies is an important technological development. Among them, 28 GHz and 38 GHz are the main potential development bands for the fifth generation mobile communication, while 19 GHz and 29 GHz are the main frequency bands for satellite communication. In wireless communication systems, the design of the transceiver is quite important and critical. This paper focuses on the design and research of key components of the transmitter. This thesis is divided into three parts: The first part (Chapter 2) is a high-image rejection up-converter mixer designed at 29 GHz for transmitters in satellite communication systems. In order to achieve better image rejection and isolation of LO signal interference in the 27~31 GHz band at the RF output port, the IQ and double balanced architecture are selected on the mixer architecture. Therefore, the four-phase input is used at the intermediate frequency and local oscillation frequency input terminals, and the RF port uses the Wilkinson power combiner to synthesize the IQ signal to produce an image suppression effect. The poly-phase filter (PPF) is used to generate four phases in the intermediate frequency portion, and the local oscillation frequency is used to generate four phases using the 90-degree coupler and 180-degree marchand balun. In addition, due to the large loss of the phase generator, an inverter amplifier is added at the intermediate frequency input to increase the overall circuit gain for system application The second part (Chapter 3) is an adjustable phase shifter designed at 29 GHz. It is fabricated using 180nm of TSMC CMOS. This tunable phase shifter combines a Switching Type Phase Shifter (STPS) and a Reflection Type Phase Shifter (RTPS) architecture. The switching type phase shifter provides 180 degrees of phase conversion, while the reflection type phase shifter uses a control bias to create a 180-degree phase adjustment, which is combined to design a 360-degree phase adjustable phase shifter. This combined architecture adds the advantages of a switching type phase shifter and a reflection type phase shifter, and complements shortcomings each other. The third part (Chapter 4) is a high PAE power amplifier designed at 38 GHz. Using TSMC's 28nm fabrication, we first analyze the 28nm process characteristics under different transistor sizes and architectures, and find the transistor size and architecture that can produce the best PAE performance to design the power amplifier. And using the transformer's power combiner to increase output power while having circuit matching and providing a bias path, this transformer power combiner reduces overall circuit losses and improves overall circuit efficiency. In addition, adding a neutralization capacitor to the circuit structure can reduce the parasitic capacitance of the transistor to make the overall circuit more stable.

參考文獻


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