利用游標尺延遲線技術實現的快速單斜率類比數位轉換器

A Fast Single Slope ADC with Vernier Delay Line Technique

林蔚峰(Wei-fong Lin)

指導教授 ： 周懷樸

國立清華大學/原子科學院/工程與系統科學系/碩士(2009年)

https://doi.org/10.6843/NTHU.2009.00766

摘要

積分型式的數位類比轉換器常用來量測核子輻射偵檢器中的脈高寬，而游標尺延遲線的技術因為可大幅減少轉換時間已被提出用來量測時間的差距。在我們提升時間解析度時，比較器的時間延遲和斜坡產生器的非線性誤差已變成改善單斜率類比數位轉換器表現的重要課題，而我們目前的工作即是在二階游標尺延遲線高精準度的時間量測架構下，發展一個能夠減少時間誤差的高精準度類比時間轉換器。
一個 9位元的類比數位轉換器用台積電互補式金氧半 0.18 微米1P6M來實現，轉換速率可達 5 Msps，而最小的時間解析度為150微微秒，量測電壓範圍為0.8~1.6V，DNL 範圍在-0.4 ~+0.5 LSB 之間，而 INL 範圍在 -0.1~+1.1 LSB 之間。

關鍵字

單斜率類比數位轉換器 ； 游標尺延遲線 ； 時間數位轉換器 ； 延遲鎖相迴路

並列摘要

Integrating type analog-to-digital converter (ADC) is commonly used for nuclear radiation spectrometers for pulse height measurement. Vernier delay line (VDL) techniques have been proposed for time measurement and can reduce conversion time significantly. With improving time resolution of VDLs, the timing error due to comparator delays and the non-linearity of ramp generator become a concern for improving the performance of the single slope ADC. The present work is to use a two-level VDL for high resolution timing measurement and to develop an amplitude-to-time converter with high precision to reduce timing errors in the time conversion process.
A 9-bit single slope ADC is realized with the process of TSMC CMOS 0.18um 1P6M. Its sample rate is 5Msps. And the minimum time resolution is about 150ps, the DNL is within -0.4~+0.5 LSB, and the INL is within -0.1~1.1 LSB.

並列關鍵字

Single Slope ADC ； Vernier Delay Line ； Time-to-Digital Converter ； Delay Lock Loop

參考文獻

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[3] B. Razavi, B.A. Wooley, “Design Technique for High-Speed, High-Resolution Comparators,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, pp. 1916-1926, Dec. 1992.

[4] P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design Second Edition, Oxford, New York, 2002.

[5] G.H. Li, H.P. Chou, “A High Resolution Time-to-Digital Converter Using Two-Level Vernier Delay Line Technique,” IEEE Nuclear Science Symposium Conference Record, Vol. 1, pp. 276-280, 2007.