二硫化鉬成長法和其電性影響之比較

Dependence of Electrical Characteristics on MoS2 Synthesis Method

鄭涵文(Han-Wen Cheng)

指導教授 ： 張翼

國立交通大學/工學院/奈米科技研究所/碩士(2019年)

摘要

本研究將探討以不同製備法的二硫化鉬材料，分別經過不同的製程處理後，再使用兩種接觸金屬Mo和Ni/Au來製作成元件，並比較各種製程效應對其造成的電性影響。近年來，許多研究都採用剝離法(Exfoliation)來製作二硫化鉬的元件，發展出許多改善元件電子特性的研究方法，雖然此製備方法快速方便且製程簡單，但因面積小且材料厚度不均勻的特性使其無法應用在大規模生產的產業鏈上。因此本研究將採用最近熱門的二硫化鉬材料合成法－化學氣相沉積法(CVD)和另一種二階段二硫化鉬合成法(2-step method)所製備的元件去進行電性比較，並分別對 (1) 2-step method MoS2元件進行ICP電漿預處理(Induce couple plasma pretreatment)和高溫退火處理(Annealing)製程。 (2) CVD MoS2 FET進行SiO2通道附蓋層(SiO2 capping layer)和高溫退火處理(Annealing)製程。期望能改善MoS2元件的材料薄片電阻率(sheet resistivity, rSH)和接觸電阻(contact resistance, RC)。結果顯示，2-step method MoS2元件經過ICP預處理和高溫退火後的rSH和RC值仍然非常高，趨近於絕緣體狀態；而CVD MoS2 FET的Capping layer則改善了元件的ID-VG電性，在300℃退火後也有些許的電性改善。經由以上的實驗結果可以得知，在初始製程階段我們必須選擇一個品質好(high quality)、缺陷少(low defect)、低rSH的材料，並在後續製程當中避免MoS2材料受環境與製程的劣化，是製作一個良好電性的MoS2元件最關鍵的步驟。

關鍵字

二硫化鉬 ； 合成法

並列摘要

In this thesis, molybdenum disulfide (MoS2) materials with different preparation methods will be discussed. After different process treatments, we choose two types of metal Mo and Ni/Au which are used to fabricate the contact metal pad and compared the electrical effects of these process. In recent years, many studies have used exfoliation to fabricate molybdenum disulfide devices and developing many research methods to improve the electrical properties of MoS2 devices. Although this preparation way is extremely quick, convenient and the process is simple, but the MoS2 film area is very tiny and the material thickness is not uniform. Above characteristics make it difficult to apply on the industrial chain of mass production. Therefore, this work will use the recently popular molybdenum disulfide material synthesis method- chemical vapor deposition (CVD) and another two-step MoS2 synthesis method to make electrical comparisons, we will separate two parts to carry out: (1) 2-step method MoS2 device was subjected to an induce couple plasma (ICP) pretreatment and an annealing process, respectively. (2) CVD MoS2 FET is covered SiO2 capping layer on channel and executed annealing process. It is desirable to improve the sheet resistivity (rSH) and contact resistance (RC) of the MoS2 device. The results show that the 2-step method MoS2 device has a very high rSH and RC values after ICP pretreatment and high temperature annealing, which is close to the insulator state due to high defect density. The capping layer of the CVD MoS2 FET improves the ID-VG electrical properties of the device. There is also improved electrical performance after annealing at 300 °C. From the above experimental results, we can summarize that in the initial process step, we need to choose a MoS2 material with high quality, low defect and low rSH. And avoiding the degradation of MoS2 material by environment and process in the subsequent process. It is the most essential procedure in manufacture a good electrical MoS2 devices.

並列關鍵字

MoS2 ； synthesis method

參考文獻

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