於現場可程式化邏輯閘陣列實現一個具有溫度補償的200皮秒解析度格式器

An FPGA-based Temperature Compensated 200-ps Resolution Multi-channel Formatter

黃陽凱(Yang-Kai Huang)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201702480

摘要

自動測試機台(ATE)被使用來測試積體電路(Integrated Circuit, IC)的性能與功能，避免缺陷的IC流入市場。格式器(Formatter)在自動測試機台裡是相當重要的核心模組，其負責將使用者定義的符號資料(Symbol Data)─測試向量(Test Vector)、符號寬度(Symbol width)、訊號格式(Signal Format)、邊緣時序(Edge Timing)等資訊組合，以產生待測電路所需的測試波形。
本論文提出的格式器支援多通道，可供應測試波形給予待測電路的多個輸入腳位進行測試。利用邊緣產生器控制器(Edge Generator Pool Controller)指派邊緣產生器池(EG-pool)，產生測試波形所需的轉態邊緣，並透過邊緣產生器排程(EG scheduling)更精確控制邊緣產生器轉態(Transition)的時間點。接著我們針對每個通道進行校準(Calibration)與對齊(Alignment)，使每個通道的輸出波形彼此有最小的歪斜(Skew)。此外，我們使用延遲值監控器(Delay Value Monitor)監測可程式化延遲線(Programmable Delay Line)的變化，並加以進行溫度補償(Temperature Compensation)，以維持邊緣產生器池產生轉態邊緣的性能。
最後，本論文實作的FPGA格式器，其支援5個通道。在校正及對齊後，通道間的最大誤差為2 ps。在進行邊緣產生器排程後邊緣擺置(Edge Placement)具備200 ps的解析度與小於50 ps的高精確度。在溫度補償部分，能有效改善溫度造成的延遲線飄移(Drift)之現象，減少溫度對邊緣擺置精確度下降的影響。

關鍵字

自動測試機台 ； 多通道格式器 ； 可程式化延遲線 ； 溫度補償 ； 現場可程式化邏輯閘陣列 ； 時序電路

並列摘要

The Automatic Test Equipment (ATE) is used to test the performance and capabilities of the integrated circuit to prevent defective IC from the market. The formatter is a very important module in ATE, it is responsible for the user-defined symbol data, including test vector, signal width, signal format and edge timings to generate the desired test signal.
In this thesis, the formatter which support multi-channel can supply the test waveforms and to give DUT of multiple input pins for the test. We used the Edge Generator Pool Controller assigning EG-pool to generate the transition edge of test waveform. At the same time, we can accurately control the EG transition by the proposed EG scheduling method. Then the output waveform of all channels get the smallest skew after we perform calibration and alignment. Besides, we use the Delay Value Monitor to monitor delay values drift in the Programmable Delay Line of EG and to perform temperature compensation, so we can maintain the edge generator pool performance for generating transition.
Finally, the FPGA formatter, which support five channels, was implemented in this thesis. The maximum skew between channels is 2 ps after the calibration and alignment. Edge Placement is possible to achieve 200 ps resolution and accuracy less than 50 ps with EG scheduling. Simultaneously, the experiment results show that using the temperature compensation can effectively improve the delay values drifted by temperature variation.

並列關鍵字

ATE ； Multi-channel Formatter ； Programmable Delay Line ； Temperature Compensation ； FPGA ； Timing Circuit

參考文獻

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[8] Jaeseok Park, et al. ”Integration of Dual Channel Timing Formatter System for High Speed Memory Test Equipment,” in International SoC Design Conference, 2012, pp. 185 – 187.

[9] Luca Mostardini, et al. “FPGA-based Low-cost Automatic Test Equipment for Digital Integrated Circuits,” in International Workshop on Intelligent Data Acquisition and Advanced Computing System: Technology and Applications, 2009, pp. 32 – 37.

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