FinFET邏輯閘之佈局以減少寄生電容電阻的影響

Exploring FinFET Cell Layout to Minimize Parasitic Impacts

陳冠綸(Chen, Guan Lun)

指導教授 ： 張彌彰

國立清華大學/電機資訊學院/電子工程研究所/碩士(2016年)

摘要

隨著半導體最小線寬縮小到奈米尺度的今日，場效電晶體的源極和汲極越來越接近，使得閥極沒有辦法完全控制通道開關，導致即使是在閥極接地的情況下也有顯著的漏電流產生。為了解決電晶體的漏電問題，科學家們提出了鰭式電晶體(FinFET)結構來增強通道的控制能力，然而FinFET的三維結構卻帶來了多餘且顯著的寄生電阻電容，這些都會對電路造成很大的影響。為了瞭解寄生電阻電容造成影響的主要因素，我們採用非對稱的FinFET模型去模擬分析。模擬結果顯示寄生電阻與電容會在源極和汲極兩端產生不同程度的影響。藉由這個結果，我們仔細研究了FinFET佈局並提出了兩種方法去減少寄生電阻對電路的影響。一個是把源極和汲極的VIA0移到中間，另一個則是增加兩極VIA0的數量，兩種方式都經過實際下線驗證成功。此外，我們也研究了非對稱FinFET佈局面積與電路效能之間的關係，不過由於佈局規定上的限制，並沒有下線做更進一步驗證與分析。

關鍵字

鰭式電晶體 ； 寄生電阻 ； 寄生電容 ； 佈局 ； 邏輯閘

並列摘要

As the feature size of the semiconductor technology shrunk to nanometer scale, the distance between source and drain of a MOSFET becomes so short such that the gate lose full control of the channel, and thus there is significant leakage current even when gate is grounded. FinFET technology has been adopted to solve this leakage problem. However, FinFET’s 3D structure incorporates significant parasitic capacitance and resistance and that can have larger impacts on circuit performance. To study the dominating factor of the impacts, asymmetric FinFET transistors have been constructed and simulated extensively. It confirms that parasitic resistance and capacitance contribute differently for the source drain terminals. Using this information, the FinFET gate layout is reviewed and two approaches to reduce the parasitic resistance impacts are proposed. One is move the VIA0 position to the center and the other is to increase the number of VIA0. Both approaches were verified by silicon test chips. Asymmetric FinFET transistor layouts that can trade off performance and area have also been developed. However, due to design rule constraints these layouts have not been verified.

並列關鍵字

FinFET ； Parasitic resistance ； Parasitic capacitance ； Layout ； Logic gate

參考文獻

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