同步多緒處理架構的動態提取引擎的設計之研究

A Study of Dynamical Fetch Engine on SMT

楊書喬(Su-Chiao Yang)

指導教授 ： 謝忠健

大同大學/電機資訊學院/資訊工程學系所/碩士(2008年)

摘要

同步多線程處理器擁有同時兼執行不同線程的能力。事實上，同步多線程被認為是一個效力強大的架構，並且被加入超純量處理器以提升它的效能。
同步多線程處理器是一個允許來自於多個不同獨立的應用程式或者是線程同時競爭有限資源的技術。提取單元已廣泛的被認為是同步多線程架構上的瓶頸，許多研究提出了多個提取策略來提升提取的效率與整體的效能。
在此篇論文中，我們提出了一個名為佇列狀態識別的提取策略來記錄每一個時脈每個線程所擁有的某些長延遲指令，並且在下一個時脈適當的選擇線程來被提取。在模擬的結果中，我們的提取策略最好可以達到30%的效能提升，並且可以減少第一層資料快取的失誤率。

關鍵字

同步多緒處理器 ； 佇列狀態識別器 ； 第一層資料快取失誤率

並列摘要

A Simultaneous Multithreading (SMT) Processor is capable of executing instructions from multiple threads in the same cycle. SMT in fact was introduced as a powerful architecture to superscalar to increase the throughput of the processor. Recently, several computer manufactures (such as Intel and IBM) have introduced their first generation SMT architecture processor.
Simultaneous Multithreading is a technique that permits multiple instructions from multiple independent applications or threads to compete limited resources each cycle. While the fetch unit has been identified as one of the major bottlenecks of SMT architecture, several fetch schemes were proposed by prior works to enhance the fetching efficiency and overall performance.
In this thesis, we propose a novel fetch policy called queue situation identifier (QSI) which counts some kind of long latency instructions of each thread each cycle then properly selects which threads to feed next cycle. Simulation results show that in best case our fetch policy can achieve 30% on speedup and also can reduce the DL1 miss rate.

並列關鍵字

Simultaneous Multithreading ； Queue Situation Identifier ； Date Cache Level 1 miss rate

參考文獻

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