矽智財權的樂高化：以特殊積體電路設計為例

Legorization of Silicon Intellectual Property: An Example of ASIC Design

陳志重(Chih-Chung Chen)

指導教授 ： 胡均立

國立交通大學/管理學院/管理學院高階主管管理碩士學程/碩士(2018年)

摘要

矽智財權的樂高化：以特殊積體電路設計為例
研究生：陳志重 指導教授：胡均立
國立交通大學
高階主管管理學程碩士班

中文摘要
越來越多新的科技概念及技術被提出來且廣泛應用於不同領域。隨著晶圓代工廠製程技術飛快的演進，芯片在單位面積裡面的容量得以大幅提升。這些因素促使積體電路的設計變得更複雜且開發時間更加的冗長。如何有效的縮短積體電路設計研發所需時間，以因應漸趨複雜的芯片設計變成了致勝因素之一。傳統的積體電路設計大部分著重在追求芯片最佳的效能，最低的功耗及最小的面積。為了達到這些訴求，很多積體電路的設計運用了很多邊際訊號或甚至直接控制的方法來達到目的。這樣的方式在封閉的嵌入式系統是一個快速且有效的方法。當芯片需要重新流片，重複使用設計模塊，除錯及驗證時候，這樣的嵌入式系統卻會有著相當的困難度及風險，最終可能造成嚴重的影響。例如: 喪失產品上市的最佳時間，消磨了客戶對產品可靠度的信心，人力及物力資源的消耗等。本篇論文訴求論點是把矽智財權積木化的設計想法運用在積體電路模塊設計上。藉由全面的SIP架構系統化，重複利用設計智慧，使得整合及驗證流程更加精簡有效的概念來縮短在研發上可能的時間消耗，以達到節省研發成本及增加設計的可靠度、生產力。

關鍵字：矽智財權、樂高化、積體電路設計

關鍵字

矽智財權 ； 樂高化 ； 積體電路設計

並列摘要

Legorization of Silicon Intellectual Property:
An Example of ASIC Design

Student: Chih-Chung Chen Advisor: Jin-Li Hu

Master Program of Management for Executives
National Chiao Tung University

Abstract
More and more modern applications launched in recent years. Also, foundries keep improving on manufacturing process to make cell density on each die increase dramatically. Those factors make ASIC (Application specific Integrated Circuit) design become more complex and time-consuming task. How to complete whole ASIC development process within a reasonable time budget becomes one of keys to win. Traditional ASIC design put focus on chasing best PPA (Performance, Power and Area) numbers. Most of ASIC designs have its own side band signals or even direct control between building blocks to get better PPA numbers. In embedded system, perhaps, it is one of good solutions, due to native closed system environment. The difficulty on building-blocks-based design will become serious, when respin, reuse, verification and debug etc. problems pop up. It will take longer time to settle down design changes and waste potential resources. For instance, miss best time to market, lose confidence from customer, invest more resources on RD. This thesis brings an idea to legorize SIP on ASIC from traditional building-blocks-based design. By its nature of well-defined system level architecture, design reuse concept, easy integration and verification methodologies to reduce possible time consumption, cost saving and increase design reliability and productivity.

Keywords: Silicon IP, Legorization, ASIC

並列關鍵字

Silicon IP ； Legorization ； ASIC

參考文獻

References

1. Jocelyn Chang, “Speeding through the ADAS market 0-60”, Texas Instruments, Dec. 2015.

https://e2e.ti.com/blogs_/b/behind_the_wheel/archive/2015/12/07/speeding-through-the-adas-market-0-60

2. Grim Yun, Heekyung Yang, Cheolseong Park, Jyungha Min, “Legorization with multi-height bricks from silhouette-fitted voxelization”, CGI’17, June 27-30, 2017, Yokohama, Japan.

3. Marketsandmarkets, “Semiconductor IP Market worth 6.22 Billion USD by 2023”, October 2017.