氮化處理與介面工程於高介電材料金氧半元件之探討

Electrical Characteristics of Metal-Oxide- Semiconductor Devices by Nitridation treatment and Interfacial Engineering on High-K Dielectrics

王晉億 ； 黃芝傑 ； 陳敏璋

《國家奈米元件實驗室奈米通訊》 24卷3期 (2017/09) Pp. 2-7

摘要

本研究主要探討由具有四方晶/立方晶結構的二氧化鋯(ZrO_2)以及氮化氧化鋁(Al_2O_3)作為緩衝層所組成的閘極高介電材料，以減少等效電容厚度(Capacitance Equivalent Thickness, CET)、漏電流密度(J_g)及介面缺陷密度(Dit)等特性。高介電的四方晶/立方晶二氧化鋯可於450℃低溫退火形成，但由於多晶結構，晶界所造成的漏電流變得嚴重許多，而我們發現於ZrO_2與Si之間插入一層Al_2O_3可以有效抑制漏電流的產生，另外在氧化層內進行氨氣(NH_3)電漿的處理，可以填補其中的氧空缺以及鈍化界面中矽的懸垂鍵(Dangling Bonds)，因此在Pt/ZrO_2/Al_2O_3/Si結構中的氧化層進行NH_3電漿處理之元件，可以得到低的J_g (3.43 ×10^(-5) Acm^(-2))以及Dit(3.35×10^(11) cm^(-2) eV^(-1))，並達到低的CET(1.09 nm)，而在熱穩定性方面也獲得大大的提升，可承受800℃的高溫製程。本研究指出NH_3電漿處理於ZrO_2/Al_2O_3之閘極介電結構可望應用於下世代奈米金氧半場效式電晶體。

關鍵字

高介電材料 ； 等效電容厚度 ； 漏電流密度 ； 金氧半場效式電晶體

並列摘要

The gate dielectric stack composed of the tetragonal/cubic ZrO_2 and Al_2O_3 buffer layer was investigated to reduce the capacitance equivalent thickness (CET), leakage current density (J_g), interfacial state density (Dit), and enhance thermal stability as well. The high-K gate stack was provided by the crystalline ZrO_2 with tetragonal/ cubic phase, in which the grain boundaries result in severe gate leakage. The insertion of the Al_2O_3 buffer layer between Si and ZrO_2 leads to the suppression of J_g. Furthermore, the NH3 plasma treatment was used to passivate the oxygen vacancies and Si dangling bonds. Therefore, the tetragonal/cubic ZrO_2 and Al_2O_3 buffer layer gate stack together with the NH3 plasma treatment device exhibited low J_g of 3.43×10^(-5) A/cm^(-2), CET of 1.09 nm, and Dit of 3.35×10^(11) cm^(-2)eV^(-1). In addition, the thermal stability of the gate stack can also be greatly improved to the high-temperature process at 800 ℃. The crystalline high-K dielectric/buffer layer gate stack has been applied to enhance the gate control for suppression of the short channel effect in FinFET devices.

並列關鍵字

High-K Dielectrics ； Capacitance Equivalent Thickness ； Leakage Current Density ； MOSFET