摘要
在繞線完後的電路上插入額外鑽孔（ RVI ）是一個形成雙倍鑽孔的普遍的作法，並且針對此作法有很多有效率的演算法被發明出來。然而，實現這些演算法往往忽視一些實際問題，因次這些常見有著極高的額外鑽孔插入比例的數據報告是沒有考慮到這些實際問題。在此論文中，我們實做在繞線完後的電路上插入額外鑽孔（RVI)演算法，在插入這些額外鑽孔時考慮到在互相連接方面的電路資訊。我們尤其注重在這些通常位於金屬層一的引腳端去形成額外鑽孔。我們還進行可靠性的RVI以提高在時間上較為關鍵的線路上的額外鑽孔插入的比例。我們把這個作法用到商業設計流程並且用商業標準元件庫去做電路合成來測試。實驗結果表明，我們的額外鑽孔插入平均提高via1 （在金屬層一和二之間的鑽孔 ）的插入比例從37.4 ％到72.1 ％ ，總共的插入比例從72.5 ％到85.8 ％ 。平均而言，在關鍵時間的線路上增加額外鑽孔插入的比例為3.6 ％ 。除此之外，在額外增加的引腳面積最小化的作法上，我們採用的方法可以減少用在引腳上金屬層一和金屬層二的面積減少3 ％ 。
並列摘要
Post-routing redundant via insertion (RVI) is an effective approach to forming double vias in a chip and effective algorithms have been invented for it. However, implementations of these algorithms often ignore some practical issues and hence constantly report exceedingly high RVI rates that are not achievable when these practical issues are considered. In this thesis, we implement a post-routing RVI algorithm that takes into account interconnect contexts during RVI. We especially focus on forming redundant vias at pin ports normally situated at metal layer 1. We also carry out reliability-driven RVI to increase RVI rates on timing critical paths. Our implementation has been ported to a commercial design flow and tested on benchmark circuits synthesized with a commercial standard cell library. Experimental results show that our context-aware RVI on average raises via1 (vias between metal layer 1 and 2) insertion rate from 37.4% to 72.1% and total insertion rate from 72.5% to 85.8%. On average, it increases RVI rate of critical paths by 3.6%. Besides, with redundant pin-area minimization, our approach reduces metal 1 and metal 2 area used for RVI at pins by 3%.