摺疊R-2R階梯式電流導引數位類比轉換器之非線性度分析與實現

Nonlinearity Analysis and Implementation of Folded R-2R Ladder-Based Current-Steering DAC

呂南谷(Nan-Ku Lu)

指導教授 ： 陳淳杰

中原大學/工學院/電子工程研究所/博士(2012年)

https://doi.org/10.6840/cycu201200365

摘要

本文呈現兩種新架構，分別稱為摺疊R-2R階梯式電流導引數位類比轉換器與虛擬二進位摺疊R-2R階梯式電流導引數位類比轉換器。並且針對R-2R階梯式電流導引數位類比轉換器、摺疊R-2R階梯式電流導引數位類比轉換器與虛擬二進位摺疊R-2R階梯式電流導引數位類比轉換器進行非線性度的學理分析，分析過程同時考慮電流非匹配度與電阻非匹配度的影響。
本文也針對虛擬二進位摺疊R-2R階梯式電流導引DAC提出一套設計流程，使設計者可快速且精準選擇電路中電阻與電流源各自所需的元件非匹配度。以DAC解析度操作於6位元為例，本作品相較於傳統R-2R階梯式電流導引DAC可節省56.25%的電阻使用量，以及減少56.25%的功率消耗。以TSMC 0.18um 1P6M製程所製造的晶片核心面積為0.042mm2，量測結果顯示DNL與INL分別為0.34LSB與0.25LSB，最大靜態功率消耗為8mW。

關鍵字

數位類比轉換器 ； R-2R階梯 ； 積分非線性度 ； 微分非線性度

並列摘要

This thesis presents two new architectures which are called folded R-2R ladder-based current-steering digital to analog converter and pseudo binary folded R-2R ladder-based current-steering digital to analog converter, respectively. A theoretical nonlinearity analysis of R-2R ladder-based current-steering digital to analog converter and proposed circuits is presented. In addition, the nonlinearities caused by the current mismatches and the resistor mismatches are also analyzed.
This thesis also presents a design flow of pseudo binary folded R-2R ladder-based current-steering digital to analog converter. The derived equations enable circuit designers to quickly select the most suitable design for their applications by calculating the required resistor mismatch and required current mismatch. In the case of 6-bit resolution, the proposed circuit can reduce the total number of required unit resistors by up to 56.25% and 56.25% power consumption compared with conventional R-2R ladder-based current-steering DAC. The measured DNL and INL are 0.34LSB and 0.25LSB, respectively. The converter consumes 8mW with 1.8V power supply. The active area of chip is less than 0.042mm2 in TSMC 0.18um 1P6M process.

並列關鍵字

Integral Nonlinearity (INL) ； R-2R ladder ； Digital to Analog Converter (DAC) ； Differential Nonlinearity (DNL)

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