一個六位元虛擬二進位摺疊R-2R階梯式電流導引數位類比轉換器設計與特性分析

A 6-bit Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter design and characteristics Analysis

詹竣宇(Chun-Yu Chan)

指導教授 ： 陳淳杰

中原大學/電機資訊學院/電子工程研究所/碩士(2017年)

https://doi.org/10.6840/cycu201700563

摘要

本篇論文設計一個六位元虛擬二進位摺疊R-2R階梯式電流導引數位類比轉換器。設計平台使用TSMC 0.18 μm 1P6M CMOS製程。在電源為1.8V的狀況下，模擬結果功率消耗為1.9913mW。在輸入頻率為 179.6875MHz時，ENOB為5.79bit，DNL為±0.011，INL為±0.012，SFDR為48.80dB。將設計完後的電路再做進一步的分析，以差動對開關與疊接式流鏡的各個MOS元件大小對於整體電路影響。

關鍵字

電流式 ； 數位類比轉換器 ； R-2R

並列摘要

This paper aims to design a 6-bit Pseudo binary folded R-2R ladder-based current-steering Digital to Analog Converter. The design platform uses TSMC 0.18-μm 1P6M CMOS. The simulation results show that the power consumption is 1.9913mW when the power supply is 1.8V. In addition, when the input frequency is set to 179.6875MHz, the ENOB is 5.79 bits, the DNL is ±0.011LSB, the INL is ±0.012LSB and the SFDR is 48.80dB, respectively. A further analysis to the designed circuit was presented by investigating the MOS device size of differential pair and current-sourse for the overall circuit impact.

並列關鍵字

current-steering ； digital-to-analog converter ； R-2R

參考文獻

[11] 楊皓翔, “一個六位元每秒二十億次取樣頻率的虛擬二進位摺疊R-2R階梯式電流導引數位類比轉換器”, 中原大學電子工程系研究所碩士班論文,2014.

[15] 曾偉信,“高速電流引導式數位類比轉換器”,交通大學電子工程系研究所博士班論文,2011.

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