使用六位元逐次逼近式類比數位轉換器作量化器回授之高解析度低功耗離散時間二階三角積分調變器

Design of a High Resolution and Low Power Discrete-Time Second-order Delta Sigma Modulator with 6-bit SAR Feedback Quantizer

陳柏劭(Po-Shao Chen)

指導教授 ： 江正雄

淡江大學/工學院/電機工程學系機器人工程碩士班/碩士(2020年)

https://doi.org/10.6846/TKU.2020.00724

摘要

類比數位轉換器(Analog-to Digital-Converter, ADC)的應用十分廣泛，且擁有許多種類，如果考慮高解析度的應用，三角積分類比數位轉換器是最佳選擇。三角積分類比數位轉換器的核心是三角積分調變器(Delta-Sigma Modulator, DSM)，為了達到更高的解析度，在設計上可以考慮提高DSM的階數或是量化器位元數，而後者的提升，會使得量化器的設計更來得不容易，且功耗要求更大。而如何在提高位元數的要求下，盡可能的設計出高解析度且低耗能的量化器，是本論文所探討之方向。

本研究為設計一個三角積分類比數位轉換器(DSM ADC)，並結合逐次逼近式類比數位轉換器(SAR ADC)作為量化器使用。相較於一般使用快閃式類比數位轉換器(FLASH ADC)為量化器，使用SAR ADC可以擁有更低的功耗，且FLASH ADC在高位元的考量下，設計不易且效能不佳，使用SAR ADC可以解決此問題，在高位元量化器的DSM實現下，更能凸顯出SAR ADC量化器及Flash ADC量化器的優劣性。

本論文所提出的三角積分調變器，使用UMC 0.18m CMOS製程，其作用電壓為1.8V，頻寬為25kHz，取樣頻率為3.2MHz，系統電壓操作範圍為0.45V 至 1.35V，SNDR可達到101.88 dB，平均功耗為833uW。

關鍵字

離散時間 ； 三角積分調變器 ； 逐次逼近式類比數位轉換器之量化器

並列摘要

The applications of Analog-to-Digital Converter (ADC) are very broad, and it has various types. When considering high resolution applications, Delta-Sigma Analog-to-Digital Converter must be the best choice. Delta-Sigma Modulator (DSM) is the core of Delta-Sigma Analog-to-Digital Converter. As for high resolution Delta-Sigma ADC considerations, there are two approaches to achieve this goal. One is to increase the order and the other is to increase quantizer bits of the SDM. The latter method will make the quantizer design become more difficult and consume more power. This research work will investigate how to design high resolution and low power quantizer while increasing the bits in the quantizer.

This work designs a high resolution DSM combined with Successive Approximation Register (SAR) ADC as the quantizer. Compared with using conventional FLASH ADC as the quantizer in a DSM, using SAR ADC will consume less power. For circuit implementation, it is difficult to design a high bit FLASH ADC, while using SAR ADC will resolve these problems. Under high bit DSM, the strength and weakness between SAR quantizer and Flash quantizer will significantly arise.

The proposed DSM was designed by UMC 0.18m CMOS technology. The chip has functional voltage of 1.8V, bandwidth of 25kHz, sampling frequency of 3.2MHz, system operation voltage ranging from 0.45V to 1.35V, SNDR of 101.88 dB and power consumption of 833uW.

並列關鍵字

Discrete-Time ； Sigma Delta Modulator ； SAR quantizer

參考文獻

[1]Chun-Yao Lu, Chang-Yu Hsieh,Hsin-Liang Chen and Jen-Shiun Chiang, "A high-resolution time-interleaved delta-sigma modulator with low oversampling," Proceedings of the 2009 12th International Symposium on Integrated Circuits, Singapore, 2009, pp. 5-8.

[2]D. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997

[3]P. Su and H. Chiueh, "The design of low-power CIFF structure second-order sigma-delta modulator," 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, 2009, pp. 377-380

[4]Behzad Razavi, Design of Analog CMOS Integrated Circuits, 2000

[5]D. Hernandez-Garduno, J. Silva-Martinez, “ Continuous-time common-mode feedback for high-speed switched-capacitor networks,” IEEE J. Solid-State Circuits, vol. 40, pp. 1610–1617, Aug. 2005