使用動態元件匹配之二階三位元差和調變器設計

THE DESIGN OF SECOND-ORDER 3-BIT DELTA-SIGMA MODULATOR USING DYNAMIC ELEMENT MATCHING METHOD

黃柏蒼(Bo-Tsang Huang)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/電機工程學系所/碩士(2004年)

摘要

在這篇論文，我們實現一個差和類比/數位轉換器。我們使用一個三位元二階調變器來增加其有效位元數，另外使用動態元件匹配法來降低對三位元回饋數位/類比轉換器線性度的要求。此外，動態元件匹配電路的設計則考慮到延遲時間對調變器的影響。
在過取樣率為200時(取樣頻率為10 MHz、訊號頻寬為25kHz)，調變器在訊號頻帶的訊號雜訊比可以達到 97dB。類比部份的設計是採用TSMC 0.35 CMOS 製程。在電源供應為3.3V時，所消耗的功率為20mW。由模擬可知，若電容匹配誤差為5%，其訊號雜訊比將降到40dB，且二次協波變大。若使用動態元件匹配電路，則訊號雜訊比可提高到80B。另外Nyquist頻帶外所不需要的雜訊，需要用降頻器來移除。在使用兩級的FIR濾波器和 8倍的降頻之後，此轉換器的訊號雜訊比為93dB，相當於15位元的解析度。

關鍵字

差和調變器

並列摘要

The design of a delta-sigma analog-to-digital converter is presented. It uses a 3-bit second-order modulator with dynamic element matching (DEM) to reduce the linearity requirements for the feedback DAC. The DEM algorithm is implemented in such a way to minimize the additional delay within the feedback loop of the modulator.
For an oversampling ratio of 200, the converter achieves a signal-to-noise ratio (SNR) of 97 dB in the signal band. The converter is sampled at 10 MHz and signal bandwidth is 25 kHz. The analog circuit design will be implemented in a TSMC 0.35 CMOS technology, and consumes 20 mW from s 3.3-V power supply. It is shown that the SNR in the signal band for 5% mismatch in DAC is degraded to 40 dB. In addition, the non-linearity of the DAC due to capacitance mismatch generates a large second harmonic distortion. If DEM is employed, the SNR would be improved to 80 dB. The unwanted noise in the spectrum above the Nyquist band can be removed by using a decimator. For a two-stage FIR filters and eight times downsampling, the overall SNR for the entire ADC is 93dB, which is equivalent to 15-bit resolution.

並列關鍵字

DELTA-SIGMA

參考文獻

[1] Eric T. King, Terri S. Fiez, “A Nyquist-Rate Delta–Sigma A/D Converter,” IEEE J. Of Solid-State Circuits, Vol. 33, No. 1, Jan. 1998.

[2] Ian Galton, Henrik T.jensen “Oversampling Paeallel Delta-Sigma Modulator A/D Conversion,” IEEE Transactions On Circuits And Aystems- Analog And Digital Signal Processing Vol 43.No12 Dec. 1996.

[3] David A. Johns, Ken Martin “Analog Integrated Circuit Design,” John Wiley & Sons, Inc.1997.

[7] Yves Geerts, Michel S. J. Steyaert,” A High-Performance Multibit CMOS ADC,” IEEE J. Of Solid-State Circuits, Vol. 35, No. 12, Dec. 2000.

[9] M.J.M. Pelgrom, et al., “Matching Properties of MOS Transistors,” IEEE J. of Solid-State Circuits, vol. 24, no. 5, pp. 1433-9, Oct. 1989.