使用前饋式架構為基礎之雙取樣四階帶通差和調變器設計

THE DESIGN OF A DOUBLE-SAMPLED FOURTH-ORDER BANDPASS DELTA-SIGMA MODULATOR BASED ON FEEDFORWARD TOPOLOGY

許志聖(Chih-Sheng Hsu)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/通訊工程研究所/碩士(2004年)

摘要

數位中頻接收器的好處是可以消除在低頻轉換介面出現的一些非線性效應。更重要的是，從中頻降至基頻是由數位電路處理，因此其抗雜訊性高、且無匹配問題。然而，中頻往往是數十MHz，因此不適合使用一般類比轉換電路。而帶通調變器應用差和調變技術可以減少載波頻帶的量化雜訊，其雜訊減少程度跟取樣頻率與兩倍訊號頻寬之比值(非兩倍載波頻率)取對數成正比。量化雜訊減少越多，其所需的超取樣比值就要越大。相較於傳統的Nyquist-rate轉換器，上述所描述的優點使帶通調變器非常適合應用在數位中頻接收機上。
在本篇論文中，我們提出一前饋式架構為基礎之雙取樣四階帶通差和調變器設計，其設計流程及相關設計軟體如下：先使用MATLAB模擬理想之系統層級電路，藉此得到最佳化的參數值。接下來用HSPICE模擬電晶體層級的電路，這樣可以加速整個設計的流程。此調變器的時脈頻率為50MHz(相當於100MHz的取樣頻率)，輸入中心頻率為25MHz、頻寬200KHz的訊號，以HSPICE所做的模擬結果顯示，在最佳化架構下，其最大訊號雜訊比是70dB、消耗功率為55.52mW。此電路是使用TSMC 0.35μm CMOS 2P4M製程技術進行模擬。

關鍵字

前饋式 ； 雙取樣 ； 帶通 ； 差和調變器

並列摘要

Digital IF receivers are an intermediate architecture toward software radio. There are two main advantages presented in such architecture. One is to avoid the nonlinear problem appearing at low frequency. The other advantage is that processing signals from IF to baseband in digital domain is better due to noise insensitivity and no matching problem for digital circuits. However, the IF frequency is usually in the range of several MHz, and analog-to-digital conversion cannot be easily achieved by a traditional architecture. Bandpass modulators, on the other hand, perform analog-to-digital conversion by reducing the in-band quantization error around the carry frequency using a notch type of noise shaping. General speaking, the in-band quantization error is related to the ratio, called oversampling ratio (OSR), between the sampling frequency and two times the bandwidth of the signal (instead of two times bandwidth of carry signal). In other word, a higher OSR value results in the less in-band quantization error. Compared to traditional Nyquist-rate converter, the above discussed advantages give a strong opportunity to employ bandpass modulator in digital IF receiver.
In this thesis, a double-sampled fourth-order bandpass delta-sigma modulator based on feedforward topology is proposed. The design flow corresponding to the CAD tools is as followings. Using MATLAB, the optimal parameters are obtained by the system level simulation. Then, the transistor level simulator (HSPICE) is used to verify the performance with these optimal parameters. The clock frequency is 50MHz (effective frequency would be 100MHz). The input signal bandwidth is 200kHz centered at 25MHz. The simulation results using HSPICE present a peak SNR of 70dB and power consumption of 55.52mW. The modulator is simulated by using the SPICE models of TSMC 0.35μm CMOS 2P4M process.

並列關鍵字

FEEDFORWARD ； DOUBLE-SAMPLED ； BANDPASS ； DELTA-SIGMA

參考文獻

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