雙路徑四階帶通差和調變器

THE DESIGN OF A DOUBLE-PATH FOURTH-ORDER BANDPASS DELTA-SIGMA MODULATOR

陳頌智(Sung-Jr Chen)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/通訊工程研究所/碩士(2006年)

摘要

中文摘要
本篇論文所研究的方向為數位中頻接收機的類比數位轉換介面，其中最主要的設計是以超取樣帶通差和調變器(oversampling delta-sigma bandpass modulator)為主要目標。傳統接收機所用的奈奎氏類比數位轉換器並不適用於數位中頻接收機的架構，因為中頻訊號往往是數十MHz，所需要的超取樣比值就要大，取樣頻率將會非常地高，而造成電路上設計的難度。因此，在此類型的接收機中使用帶通差和調變器，由於其雜訊減少程度跟取樣頻率與兩倍訊號頻寬之比值取對數成正比，因此可以使用較低的取樣頻率，將訊號直接在中頻做數位化，而減少量化的雜訊，和避免非理想特性。有許多此類型的系統都成功的在文獻中被提出，證明了上述所提的優點。因此，帶通差和調變器在數位中頻接收機或甚至在未來的數位射頻接收機設計中扮演重要的角色。

本篇論文為使用具有低溫度雜訊和不易受電容匹配度影響的切換電容雙迴路積分濾波器的雙路徑四階帶通差和調變器。此調變器的每條路徑，時脈頻率為50MHz，相當於100MHz的有效取樣頻率，輸入為中心頻率25MHz、頻寬200kHz的訊號。設計流程和相關設計軟體如下：先使用MATLAB的SIMULINK模擬理想的系統層級電路，找出最佳化的各項參數值。再以HSPICE模擬電晶體層級的電路。以TSMC 0.35μm CMOS 2P4M製程參數進行模擬，消耗功率約55mW，其最大訊號雜訊比約為70 dB。

關鍵字

差和調變器

並列摘要

The research purpose of this thesis is digital IF A/D converter. An oversampling bandpass delta-sigma modulator has been designed. Nyquist-rate A/D converters used in the conventional receiver is not suitable for digital IF receiver structure. Because IF signal is often several 10MHz, the oversampling rate will be great, and the analog circuit at a high sampling frequency is very difficult to realize with low power consumption. Therefore, the use of a bandpass delta-sigma modulator has been adopt to directly digitalize the IF signal by lower sampling frequency (usually 4 times of the center frequency). In this kind of receiver, the in-band quantization error is related to the oversampling ratio. These can reduce quantization error, and avoid non-idealities characteristic. A lot of system architectures were proposed in the literature, and prove the above advantages. Therefore, bandpass delta-sigma modulators play an important role in the digital IF receiver or possibly digital RF receiver in the future.

In this thesis, a double-path fourth-order bandpass delta-sigma modulator was built based on a switched-capacitor (SC) filter with lower thermal noise and less sensitive to the capacitor mismatch. Two interleaved paths clocked at 50MHz. The effective sampling frequency is 100 MHz. A 200 kHz bandwidth signal is centered at 25 MHz. The design flow corresponding to the CAD tools is as followings. The Delta-Sigma Toolbox for MATLAB and SIMULINK are used for defining the valid building block specifications. Then, HSPICE is used for transistor-level simulations. The modulator is simulated by using the HSPICE models of TSMC 0.35μm CMOS 2P4M process. The power consumption is 55mW. The peak signal-to-noise ratio is about 70 dB.

並列關鍵字

delta-sigma modulator

參考文獻

[1] T. Salo, S. Lindfors, and K. A. I. Halonen, “A Double-Sampling SC-Resonator for Low Voltage Bandpass ΔΣ-Modulators,” IEEE Trans. on Circuits Syst. II, Vol. 49, no. 7, pp.737-747, Dec. 2002.

[2] S. I. Liu, C. H. Kuo, R. Y. Tsai, and J. Wu, “A Double-Sampling Pseudo-Two-Path Bandpass ΔΣ Modulator,” IEEE J. Solid-State Circuits, Vol. 35, pp.276-280, Feb. 2000.

[3] A. Hairapetian, “An 81-MHz IF Receiver in CMOS,” IEEE J. Solid-State Circuits, Vol. 31, pp.1981-1986, Dec. 1996.

[4] F. Francesconi, V. Liberali, and F. Maloberti, “A Band-Pass Sigma-Delta Modulator Architecture for Digital Radio,” Circuits and Systems, Vol. 2, pp.885-888, Aug 1995.

[5] B. S. Song, “A Fourth-Order Bandpass Delta-Sigma Modulator with Reduced Number of Op Amps,” IEEE J. Solid-State Circuits, Vol. 30, pp.1309-1315, Dec. 1995.