六位元快閃式類比數位轉換器 暨 十位元電壓切割式數位類比轉換器設計

Design of 6-bit Flash ADC and 10-bit voltage-segmented DAC

黃筑琳(Ju-Lin Huang)

指導教授 ： 盧志文

國立暨南國際大學/科技學院/電機工程學系/碩士(2010年)

摘要

本論文中分別提出了兩種轉換器電路，第一種為6-bit快閃式類比數位轉換器，第二種則是應用於薄膜液晶顯示器(TFT- LCD)源極驅動器上之10-bit電壓式數位類比轉換器。 第一個電路為利用TSMC 0.18μm的製程設計一個6-bit的快閃式類比數位轉換器，其取樣頻率2GHz，使用電源供給電壓為1.8V。本論文電路架構採全差動的方式來提升系統整體的效能，其包含線性度佳的追蹤保持電路，有重置開關的放大器，及在比較器輸出端加入等效二極體的電晶體，來限制比較器的輸出振幅。 第二個電路為利用TSMC 0.35μm的製程設計一個10-bit 數位類比轉換器。吾人提出一個新的電壓切割式數位類比轉換器，其包含一個內嵌4-bit DAC OP。首先兩個鄰近的電壓VH 與VL由兩組6 bit tree decoder取出，接著內嵌4-bit DAC OP將此電位差切割成16個電壓位階，以達成10 bit的解析度。其應用於液晶顯示器之源極驅動器，可節省薄膜液晶顯示器(TFT-LCD)晶片佈局面積超過一半以上，進而達到低成本的目的。

關鍵字

類比數位轉換器 ； 數位類比轉換器

並列摘要

Two converters are proposed in this thesis. The first one is a 6-bit flash analog-to-digital converter (ADC), and the second one is a 10-bit voltage-type digital-to-analog converter (DAC) for Thin Film Transistor Liquid Crystal Display (TFT-LCD) source driver.

The 6-bit flash ADC is designed in TSMC 0.18μm process technology. The sampling rate is 2GSapmle/s, and the supply voltage is 1.8 Volt. In this work, the “fully differential” structure is adopted and each sub-circuit is well-designed (sophisticated designed) to get more benefit of the overall performance, including a track-and-hold circuit with better linearity, preamplifiers with the reset switches, and the comparator with diode-connected transistors added at the output to limit the output swing.

The second circuit, a 10-bit DAC, is designed in TSMC 0.35μm process technology. A new voltage-segmented DAC which combines a 4-bit DAC embedded operational amplifier is proposed. Two adjacent voltage levels, VH and VL, are selected from two 6-bit tree decoders, and then the 4-bit DAC embedded operational amplifier divides this voltage range into 16 segments. As a result, the 10-bits resolution can be achieved by this architecture. The source driver of LCD displayers implemented with the proposed 10-bit DAC shrinks the layout by more than 50% and greatly reduces costs.

並列關鍵字

Analog-to-Digital Convertor ； digital-to- Analog Convertor

參考文獻

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[02] X. Jiang and M. C. F. Chang, “A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging,” IEEE J. Solid-State Circuit, vol. 40,pp.532-535,Feb. 2005.

[03] K. Uyttenhove and M. S. J. Steyaert, “A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-um CMOS,” IEEE J. Solid-State Circuit, vol. 38,pp.1115-1122, July. 2003.

[04] P. Scholtens and M. Vertregt, “A 6-b 1.6-Gsamples Flash ADC in 0.18-um CMOS Using Averaging Termination,” IEEE J. Solid-State Circuit, vol. 37, pp. 1599-1609,Dec. 2002.

[05] Hairong Yu, Student Member, IEEE,and Mau-Chung Frank Chang, Fellow,IEEE,” A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS’,IEEE Transactions on circuits and systems-II : Eepress Briefs,vol.55, no.7, July 2008.