高速八位元二階段式類比數位轉換器

本論文應用二階段式類比數位轉換器已達到高速效果。此轉換器架構的第一級是由快閃式轉換器組成，第二級是由內插式轉換器組成。將包含12%重疊範圍的8位元精準度轉換器分開處理：第一級處理較高的3.36位元，第二及處理較低的5位元。相較於較常見的安排方式，這裡在第一級轉換器的部份減少了6個轉換點，這可降低取樣保持電路的負載進而增加速度。然而，這樣的設計對於放大器的偏移電壓容忍度較小。雖然利用消除偏移電壓的技巧可以降低對於偏移電壓的要求，但是大的負載電容會減低效果。因此這裡也對於插模式及單端式偏移電壓補償加以分析，此分析有助於預測補償錯誤的大小，使得在達成偏移電壓容許範圍不至於有超乎規格的設計。

關鍵字

八位元；數位類比轉換器；二階段式

並列摘要

A two-step ADC is proposed for high speed application. The architecture of the coarse ADC is a flash-type ADC, and the fine ADC is an interpolation ADC. The 8-bit resolution of the ADC is divided into 3.36-bit in coarse ADC and 5-bit in fine ADC with 12% overlap. Comparing with conventional method, this work reduces 6 transition points in coarse ADC to decrease the loading of T/H and improve speed. However, less offset tolerance is required in coarse ADC comparators. Although offset cancellation techniques can be employed to relax the requirement, large parasitic capacitance would reduce the cancellation effectiveness. Detailed analysis for differential mode and single ended offset compensation methods will be given to predict the compensation error and to achieve the required offset constraint without over-designing.

並列關鍵字

8-bit ； two-step ； ADC

參考文獻

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國際替代計量

高速八位元二階段式類比數位轉換器

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